GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v'
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v'
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v'
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v'
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd'
Analyzing entity 'aes3rx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd":14)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd":39)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd'
Analyzing entity 'i2s_deser'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd":17)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd":35)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd'
Analyzing entity 'i2s_quad_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd":33)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd'
Analyzing entity 'i2s_quad_transmitter'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd":42)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd'
Analyzing entity 'spdif_transmitter'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd":12)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd":21)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd'
Analyzing entity 'ultranet_rx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd":37)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd'
Analyzing entity 'ultranet_serializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd":6)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd":26)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd'
Analyzing entity 'ultranet_tx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd":18)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd'
Analyzing entity 'ultranet_rx_demux'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd":12)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd":36)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd'
Analyzing entity 'ultranet_rx_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd":45)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd'
Analyzing entity 'aes3tx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":11)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":32)
WARN  (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":135)
Compiling module 'top'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":2)
Compiling module 'gowin_rpll_245'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10)
Compiling module 'main_rx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":2)
Switching to VHDL mode to elaborate design unit 'aes3rx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":35)
Processing 'aes3rx(Behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd":14)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":35)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":50)
Processing 'ultranet_rx_clocks(Behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":50)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":70)
Processing 'ultranet_rx_deserializer(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":70)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":98)
Processing 'ultranet_rx_demux(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd":12)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":98)
Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":121)
Processing 'i2s_quad_transmitter(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":121)
Compiling module 'main_tx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":2)
Switching to VHDL mode to elaborate design unit 'ultranet_tx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":38)
Processing 'ultranet_tx_clocks(Behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":38)
Switching to VHDL mode to elaborate design unit 'i2s_quad_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":75)
Processing 'i2s_quad_deserializer(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":75)
Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":99)
Processing 'ultranet_serializer(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd":6)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":99)
Switching to VHDL mode to elaborate design unit 'aes3tx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":114)
Processing 'aes3tx(behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":11)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":114)
NOTE  (EX0101) : Current top module is "top"
WARN  (EX0211) : The output port "debug_4" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":20)
WARN  (EX0211) : The output port "debug_2" of module "top" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":44)
[5%] Running netlist conversion ...
WARN  (CV0016) : Input sys_clk is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":3)
WARN  (CV0016) : Input aes3_rx is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":6)
WARN  (CV0016) : Input sfp_rx is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":7)
WARN  (CV0016) : Input ultranet_rx_2 is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":9)
WARN  (CV0016) : Input key_2 is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":40)
WARN  (CV0016) : Input key_3 is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":41)
Running device independent optimization ...
WARN  (DI0019) : Merging user defined instance "main_tx_inst2/transmitter/bit_counter[5:0]" to instance "main_tx_inst/transmitter/bit_counter[5:0]", because they are equivalent. If you want to keep the instance, please apply property constraint syn_preserve = 1 on it("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":50)
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "ultranet_tx_clocks" instantiated to "clocks" is swept in optimizing("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":30)
WARN  (NL0002) : The module "i2s_quad_deserializer" instantiated to "deserializer" is swept in optimizing("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":53)
WARN  (NL0002) : The module "ultranet_serializer" instantiated to "serializer" is swept in optimizing("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":82)
[95%] Generate netlist file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg" completed
WARN  (CK3000) : Can't calculate clocks' relationship between: "main_rx_1_inst/receiver/aes3_bclk" and "pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk"
WARN  (CK3000) : Can't calculate clocks' relationship between: "pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk" and "main_rx_1_inst/receiver/aes3_bclk"
[100%] Generate report file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project_syn.rpt.html" completed
GowinSynthesis finish
