# Timing Messages

Report Title | Timing Analysis Report
Design File | C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
Physical Constraints File | C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst
Timing Constraint File | C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc
Tool Version | V1.9.10.03 Education (64-bit)
Part Number | GW1NR-LV9QN88PC6/I5
Device | GW1NR-9
Device Version | C
Created Time | Tue Mar 18 23:31:42 2025
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C C6/I5
Hold Delay Model | Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed | 6994
Numbers of Endpoints Analyzed | 3272
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 422
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
1 | i2s_in_sclk | Base | 40.690 | 24.576 | 0.000 | 20.345 |  |  | i2s_in_sclk_ibuf/I
2 | main_rx_1_inst/aes3_bclk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | main_rx_1_inst/receiver/sclk_s0/Q
3 | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Generated | 4.069 | 245.760 | 0.000 | 2.035 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUT
4 | pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Generated | 4.069 | 245.760 | 0.000 | 2.035 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTP
5 | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Generated | 8.138 | 122.880 | 0.000 | 4.069 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTD
6 | pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 12.207 | 81.920 | 0.000 | 6.104 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTD3

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | i2s_in_sclk | 24.576(MHz) | 76.896(MHz) | 5 | TOP
2 | main_rx_1_inst/aes3_bclk | 50.000(MHz) | 154.505(MHz) | 4 | TOP
3 | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | 245.760(MHz) | 178.707(MHz) | 3 | TOP
4 | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | 122.880(MHz) | 104.205(MHz) | 4 | TOP

#### No timing paths to get frequency of pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
i2s_in_sclk | Setup | 0.000 | 0
i2s_in_sclk | Hold | 0.000 | 0
main_rx_1_inst/aes3_bclk | Setup | 0.000 | 0
main_rx_1_inst/aes3_bclk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Setup | -193.542 | 411
pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Setup | -7.559 | 11
pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -1.527 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_17_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.196
2 | -1.468 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_22_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.137
3 | -1.458 | main_rx_1_inst/transmitter/bit_counter_0_s3/Q | main_rx_1_inst/transmitter/sdout_1_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 8.138 | 0.000 | 9.196
4 | -1.452 | main_rx_1_inst/transmitter/bit_counter_0_s3/Q | main_rx_1_inst/transmitter/sdout_3_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 8.138 | 0.000 | 9.190
5 | -1.444 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_23_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.113
6 | -1.393 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_6_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.062
7 | -1.393 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_20_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.062
8 | -1.388 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_0_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.057
9 | -1.374 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_3_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.043
10 | -1.369 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_4_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.038
11 | -1.369 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_12_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.038
12 | -1.360 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_9_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.029
13 | -1.300 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_21_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.969
14 | -1.249 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_1_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.918
15 | -1.249 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_5_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.918
16 | -1.243 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_15_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.912
17 | -1.238 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_10_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.907
18 | -1.220 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_8_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.889
19 | -1.185 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_11_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.854
20 | -1.147 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_7_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.816
21 | -1.134 | main_rx_1_inst/transmitter/bit_counter_0_s3/Q | main_rx_1_inst/transmitter/sdout_2_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 8.138 | 0.000 | 8.872
22 | -1.083 | main_tx_inst/serializer/channel_cnt_2_s1/Q | main_tx_inst/serializer/ch_out_18_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.752
23 | -1.060 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_14_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.729
24 | -1.060 | main_tx_inst/serializer/channel_cnt_1_s3/Q | main_tx_inst/serializer/ch_out_19_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 4.729
25 | -1.044 | main_tx_inst/clocks/i2s_lrclk_s2/Q | main_tx_inst/deserializer/sample_ch_4_l_buf_0_s0/CE | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | -0.399 | 5.439

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.142 | main_tx_inst/clocks/aes_lrclk_s2/Q | main_tx_inst/serializer/zaes_lrck_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.267
2 | 0.558 | main_rx_1_inst/clocks/bsync_pos_edge_s0/Q | main_rx_1_inst/clocks/i2s_bclk_s2/SET | main_rx_1_inst/aes3_bclk:[R] | main_rx_1_inst/aes3_bclk:[R] | 0.000 | 0.000 | 0.571
3 | 0.561 | main_rx_1_inst/deserializer/bsync_pos_edge_s0/Q | main_rx_1_inst/deserializer/channel_counter_0_s0/RESET | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.573
4 | 0.565 | main_rx_1_inst/clocks/zzaes_lrclk_s0/Q | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/RESET | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.577
5 | 0.568 | main_rx_1_inst/receiver/aes3_clk_s0/Q | main_rx_1_inst/receiver/sync_cnt_4_s0/CE | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.581
6 | 0.587 | main_rx_1_inst/clocks/zzbsync_s0/Q | main_rx_1_inst/clocks/bsync_pos_edge_s0/RESET | main_rx_1_inst/aes3_bclk:[R] | main_rx_1_inst/aes3_bclk:[R] | 0.000 | 0.000 | 0.599
7 | 0.594 | main_rx_1_inst/receiver/aes3_clk_s0/Q | main_rx_1_inst/receiver/sync_cnt_2_s0/CE | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.607
8 | 0.594 | main_rx_1_inst/receiver/aes3_clk_s0/Q | main_rx_1_inst/receiver/sync_cnt_3_s0/CE | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.607
9 | 0.671 | main_tx_inst/clocks/i2s_bclk_s2/Q | main_tx_inst/deserializer/zbclk_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.796
10 | 0.708 | main_tx_inst/deserializer/lrck_neg_edge_s4/Q | main_tx_inst/deserializer/lrck_neg_edge_s4/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
11 | 0.708 | main_rx_1_inst/transmitter/bit_counter_1_s3/Q | main_rx_1_inst/transmitter/bit_counter_1_s3/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
12 | 0.708 | main_rx_1_inst/transmitter/bclk_neg_edge_s4/Q | main_rx_1_inst/transmitter/bclk_neg_edge_s4/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
13 | 0.708 | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0/Q | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
14 | 0.708 | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0/Q | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
15 | 0.708 | main_rx_1_inst/receiver/reg_clk_period_0_s0/Q | main_rx_1_inst/receiver/reg_clk_period_0_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
16 | 0.708 | main_rx_1_inst/receiver/sync_cnt_5_s0/Q | main_rx_1_inst/receiver/sync_cnt_5_s0/D | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
17 | 0.708 | main_tx_inst2/transmitter/data_biphase_s1/Q | main_tx_inst2/transmitter/data_biphase_s1/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
18 | 0.708 | main_tx_inst/clocks/aes_lrclk_s2/Q | main_tx_inst/clocks/aes_lrclk_s2/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
19 | 0.708 | main_tx_inst/clocks/count_aes_lrclk_0_s0/Q | main_tx_inst/clocks/count_aes_lrclk_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
20 | 0.708 | main_tx_inst/clocks/count_i2s_lrclk_0_s0/Q | main_tx_inst/clocks/count_i2s_lrclk_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
21 | 0.708 | main_rx_1_inst/clocks/count_i2s_bclk_0_s0/Q | main_rx_1_inst/clocks/count_i2s_bclk_0_s0/D | main_rx_1_inst/aes3_bclk:[R] | main_rx_1_inst/aes3_bclk:[R] | 0.000 | 0.000 | 0.708
22 | 0.709 | main_tx_inst2/transmitter/frame_counter_0_s0/Q | main_tx_inst2/transmitter/frame_counter_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.709
23 | 0.709 | main_tx_inst/transmitter/data_biphase_s1/Q | main_tx_inst/transmitter/data_biphase_s1/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.709
24 | 0.709 | main_tx_inst/transmitter/frame_counter_0_s0/Q | main_tx_inst/transmitter/frame_counter_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.709
25 | 0.709 | main_tx_inst/transmitter/bit_counter_0_s0/Q | main_tx_inst/transmitter/bit_counter_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.709

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/zzbsync_s0
2 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_2_r_6_s0
3 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_1_l_14_s0
4 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_2_l_6_s0
5 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_l_14_s0
6 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_l_6_s0
7 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_l_2_s0
8 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_l_0_s0
9 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_4_l_23_s0
10 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_l_1_s0

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -1.527
Data Arrival Time | 7.927
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_17_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[3][A] | main_tx_inst/serializer/n285_s6/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[3][A] | main_tx_inst/serializer/n285_s6/F
7.269 | 2.455 | tNET | FF | 1 | R12C25[2][A] | main_tx_inst/serializer/n387_s10/S0
7.741 | 0.472 | tINS | FR | 1 | R12C25[2][A] | main_tx_inst/serializer/n387_s10/O
7.741 | 0.000 | tNET | RR | 1 | R12C25[2][B] | main_tx_inst/serializer/n387_s5/I1
7.918 | 0.177 | tINS | RR | 1 | R12C25[2][B] | main_tx_inst/serializer/n387_s5/O
7.927 | 0.009 | tNET | RR | 1 | R12C25[2][B] | main_tx_inst/serializer/ch_out_17_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C25[2][B] | main_tx_inst/serializer/ch_out_17_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R12C25[2][B] | main_tx_inst/serializer/ch_out_17_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 24.539%; route: 3.462, 66.639%; tC2Q: 0.458, 8.821%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path2

Path Summary:

Slack | -1.468
Data Arrival Time | 7.868
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_22_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.506 | 1.206 | tNET | FF | 1 | R12C26[3][A] | main_tx_inst/serializer/n382_s13/I2
7.532 | 1.026 | tINS | FR | 1 | R12C26[3][A] | main_tx_inst/serializer/n382_s13/F
7.532 | 0.000 | tNET | RR | 1 | R12C26[3][A] | main_tx_inst/serializer/n382_s9/I0
7.682 | 0.150 | tINS | RR | 1 | R12C26[3][A] | main_tx_inst/serializer/n382_s9/O
7.682 | 0.000 | tNET | RR | 1 | R12C26[2][B] | main_tx_inst/serializer/n382_s5/I0
7.859 | 0.177 | tINS | RR | 1 | R12C26[2][B] | main_tx_inst/serializer/n382_s5/O
7.868 | 0.009 | tNET | RR | 1 | R12C26[2][B] | main_tx_inst/serializer/ch_out_22_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C26[2][B] | main_tx_inst/serializer/ch_out_22_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R12C26[2][B] | main_tx_inst/serializer/ch_out_22_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.452, 47.733%; route: 2.227, 43.345%; tC2Q: 0.458, 8.922%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path3

Path Summary:

Slack | -1.458
Data Arrival Time | 11.870
Data Required Time | 10.411
From | main_rx_1_inst/transmitter/bit_counter_0_s3
To | main_rx_1_inst/transmitter/sdout_1_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.673 | 0.244 | tNET | RR | 1 | R7C40[0][A] | main_rx_1_inst/transmitter/bit_counter_0_s3/CLK
3.132 | 0.458 | tC2Q | RF | 101 | R7C40[0][A] | main_rx_1_inst/transmitter/bit_counter_0_s3/Q
5.123 | 1.991 | tNET | FF | 1 | R11C31[2][B] | main_rx_1_inst/transmitter/n1114_s89/I2
5.749 | 0.626 | tINS | FF | 1 | R11C31[2][B] | main_rx_1_inst/transmitter/n1114_s89/F
5.749 | 0.000 | tNET | FF | 1 | R11C31[2][A] | main_rx_1_inst/transmitter/n1114_s75/I1
5.898 | 0.149 | tINS | FF | 1 | R11C31[2][A] | main_rx_1_inst/transmitter/n1114_s75/O
5.898 | 0.000 | tNET | FF | 1 | R11C31[2][B] | main_rx_1_inst/transmitter/n1114_s61/I1
6.061 | 0.163 | tINS | FF | 1 | R11C31[2][B] | main_rx_1_inst/transmitter/n1114_s61/O
7.359 | 1.299 | tNET | FF | 1 | R9C34[3][A] | main_rx_1_inst/transmitter/n1133_s1/I1
7.985 | 0.626 | tINS | FF | 1 | R9C34[3][A] | main_rx_1_inst/transmitter/n1133_s1/F
8.806 | 0.821 | tNET | FF | 1 | R9C36[3][B] | main_rx_1_inst/transmitter/n1133_s0/I0
9.432 | 0.626 | tINS | FF | 1 | R9C36[3][B] | main_rx_1_inst/transmitter/n1133_s0/F
11.870 | 2.437 | tNET | FF | 1 | IOR15[A] | main_rx_1_inst/transmitter/sdout_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
8.138 | 8.138 |  |  |  |  | active clock edge time
8.138 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
10.567 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
10.811 | 0.244 | tNET | RR | 1 | IOR15[A] | main_rx_1_inst/transmitter/sdout_1_s0/CLK
10.411 | -0.400 | tSu |  | 1 | IOR15[A] | main_rx_1_inst/transmitter/sdout_1_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 8.138
Logic Level | 4
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.190, 23.814%; route: 6.548, 71.202%; tC2Q: 0.458, 4.984%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path4

Path Summary:

Slack | -1.452
Data Arrival Time | 11.863
Data Required Time | 10.411
From | main_rx_1_inst/transmitter/bit_counter_0_s3
To | main_rx_1_inst/transmitter/sdout_3_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.673 | 0.244 | tNET | RR | 1 | R7C40[0][A] | main_rx_1_inst/transmitter/bit_counter_0_s3/CLK
3.132 | 0.458 | tC2Q | RF | 101 | R7C40[0][A] | main_rx_1_inst/transmitter/bit_counter_0_s3/Q
5.459 | 2.328 | tNET | FF | 1 | R13C34[2][B] | main_rx_1_inst/transmitter/n1102_s55/I2
6.558 | 1.099 | tINS | FF | 1 | R13C34[2][B] | main_rx_1_inst/transmitter/n1102_s55/F
6.558 | 0.000 | tNET | FF | 1 | R13C34[2][A] | main_rx_1_inst/transmitter/n1102_s53/I1
6.707 | 0.149 | tINS | FF | 1 | R13C34[2][A] | main_rx_1_inst/transmitter/n1102_s53/O
6.707 | 0.000 | tNET | FF | 1 | R13C34[2][B] | main_rx_1_inst/transmitter/n1102_s49/I1
6.870 | 0.163 | tINS | FF | 1 | R13C34[2][B] | main_rx_1_inst/transmitter/n1102_s49/O
7.854 | 0.984 | tNET | FF | 1 | R11C36[3][A] | main_rx_1_inst/transmitter/n1135_s2/I1
8.880 | 1.026 | tINS | FR | 1 | R11C36[3][A] | main_rx_1_inst/transmitter/n1135_s2/F
9.299 | 0.419 | tNET | RR | 1 | R11C37[3][B] | main_rx_1_inst/transmitter/n1135_s0/I1
9.925 | 0.626 | tINS | RF | 1 | R11C37[3][B] | main_rx_1_inst/transmitter/n1135_s0/F
11.863 | 1.938 | tNET | FF | 1 | IOR14[A] | main_rx_1_inst/transmitter/sdout_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
8.138 | 8.138 |  |  |  |  | active clock edge time
8.138 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
10.567 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
10.811 | 0.244 | tNET | RR | 1 | IOR14[A] | main_rx_1_inst/transmitter/sdout_3_s0/CLK
10.411 | -0.400 | tSu |  | 1 | IOR14[A] | main_rx_1_inst/transmitter/sdout_3_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 8.138
Logic Level | 4
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 3.063, 33.329%; route: 5.669, 61.683%; tC2Q: 0.458, 4.987%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path5

Path Summary:

Slack | -1.444
Data Arrival Time | 7.844
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_23_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][A] | main_tx_inst/serializer/n285_s8/I1
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][A] | main_tx_inst/serializer/n285_s8/F
6.482 | 1.668 | tNET | FF | 1 | R11C26[2][A] | main_tx_inst/serializer/n381_s14/I2
7.508 | 1.026 | tINS | FR | 1 | R11C26[2][A] | main_tx_inst/serializer/n381_s14/F
7.508 | 0.000 | tNET | RR | 1 | R11C26[2][A] | main_tx_inst/serializer/n381_s13/I0
7.658 | 0.150 | tINS | RR | 1 | R11C26[2][A] | main_tx_inst/serializer/n381_s13/O
7.658 | 0.000 | tNET | RR | 1 | R11C26[2][B] | main_tx_inst/serializer/n381_s5/I1
7.835 | 0.177 | tINS | RR | 1 | R11C26[2][B] | main_tx_inst/serializer/n381_s5/O
7.844 | 0.009 | tNET | RR | 1 | R11C26[2][B] | main_tx_inst/serializer/ch_out_23_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C26[2][B] | main_tx_inst/serializer/ch_out_23_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C26[2][B] | main_tx_inst/serializer/ch_out_23_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.979, 38.709%; route: 2.675, 52.327%; tC2Q: 0.458, 8.965%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path6

Path Summary:

Slack | -1.393
Data Arrival Time | 7.793
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_6_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.644 | 1.344 | tNET | FF | 1 | R8C20[3][A] | main_tx_inst/serializer/n398_s13/I2
7.466 | 0.822 | tINS | FF | 1 | R8C20[3][A] | main_tx_inst/serializer/n398_s13/F
7.466 | 0.000 | tNET | FF | 1 | R8C20[3][A] | main_tx_inst/serializer/n398_s9/I0
7.615 | 0.149 | tINS | FF | 1 | R8C20[3][A] | main_tx_inst/serializer/n398_s9/O
7.615 | 0.000 | tNET | FF | 1 | R8C20[2][B] | main_tx_inst/serializer/n398_s5/I0
7.778 | 0.163 | tINS | FF | 1 | R8C20[2][B] | main_tx_inst/serializer/n398_s5/O
7.793 | 0.015 | tNET | FF | 1 | R8C20[2][B] | main_tx_inst/serializer/ch_out_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R8C20[2][B] | main_tx_inst/serializer/ch_out_6_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R8C20[2][B] | main_tx_inst/serializer/ch_out_6_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 44.116%; route: 2.370, 46.829%; tC2Q: 0.458, 9.055%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path7

Path Summary:

Slack | -1.393
Data Arrival Time | 7.793
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_20_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.644 | 1.344 | tNET | FF | 1 | R12C21[3][A] | main_tx_inst/serializer/n384_s13/I2
7.466 | 0.822 | tINS | FF | 1 | R12C21[3][A] | main_tx_inst/serializer/n384_s13/F
7.466 | 0.000 | tNET | FF | 1 | R12C21[3][A] | main_tx_inst/serializer/n384_s9/I0
7.615 | 0.149 | tINS | FF | 1 | R12C21[3][A] | main_tx_inst/serializer/n384_s9/O
7.615 | 0.000 | tNET | FF | 1 | R12C21[2][B] | main_tx_inst/serializer/n384_s5/I0
7.778 | 0.163 | tINS | FF | 1 | R12C21[2][B] | main_tx_inst/serializer/n384_s5/O
7.793 | 0.015 | tNET | FF | 1 | R12C21[2][B] | main_tx_inst/serializer/ch_out_20_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C21[2][B] | main_tx_inst/serializer/ch_out_20_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R12C21[2][B] | main_tx_inst/serializer/ch_out_20_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 44.116%; route: 2.370, 46.829%; tC2Q: 0.458, 9.055%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path8

Path Summary:

Slack | -1.388
Data Arrival Time | 7.788
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_0_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/F
7.130 | 2.316 | tNET | FF | 1 | R13C17[3][A] | main_tx_inst/serializer/n404_s9/S0
7.602 | 0.472 | tINS | FR | 1 | R13C17[3][A] | main_tx_inst/serializer/n404_s9/O
7.602 | 0.000 | tNET | RR | 1 | R13C17[2][B] | main_tx_inst/serializer/n404_s5/I0
7.779 | 0.177 | tINS | RR | 1 | R13C17[2][B] | main_tx_inst/serializer/n404_s5/O
7.788 | 0.009 | tNET | RR | 1 | R13C17[2][B] | main_tx_inst/serializer/ch_out_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R13C17[2][B] | main_tx_inst/serializer/ch_out_0_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R13C17[2][B] | main_tx_inst/serializer/ch_out_0_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 25.215%; route: 3.323, 65.721%; tC2Q: 0.458, 9.064%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path9

Path Summary:

Slack | -1.374
Data Arrival Time | 7.774
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_3_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/F
7.116 | 2.302 | tNET | FF | 1 | R9C17[3][A] | main_tx_inst/serializer/n401_s9/S0
7.588 | 0.472 | tINS | FR | 1 | R9C17[3][A] | main_tx_inst/serializer/n401_s9/O
7.588 | 0.000 | tNET | RR | 1 | R9C17[2][B] | main_tx_inst/serializer/n401_s5/I0
7.765 | 0.177 | tINS | RR | 1 | R9C17[2][B] | main_tx_inst/serializer/n401_s5/O
7.774 | 0.009 | tNET | RR | 1 | R9C17[2][B] | main_tx_inst/serializer/ch_out_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C17[2][B] | main_tx_inst/serializer/ch_out_3_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C17[2][B] | main_tx_inst/serializer/ch_out_3_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 25.283%; route: 3.310, 65.628%; tC2Q: 0.458, 9.089%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path10

Path Summary:

Slack | -1.369
Data Arrival Time | 7.769
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.808 | 1.508 | tNET | FF | 1 | R9C25[3][A] | main_tx_inst/serializer/n400_s13/I2
7.433 | 0.625 | tINS | FR | 1 | R9C25[3][A] | main_tx_inst/serializer/n400_s13/F
7.433 | 0.000 | tNET | RR | 1 | R9C25[3][A] | main_tx_inst/serializer/n400_s9/I0
7.583 | 0.150 | tINS | RR | 1 | R9C25[3][A] | main_tx_inst/serializer/n400_s9/O
7.583 | 0.000 | tNET | RR | 1 | R9C25[2][B] | main_tx_inst/serializer/n400_s5/I0
7.760 | 0.177 | tINS | RR | 1 | R9C25[2][B] | main_tx_inst/serializer/n400_s5/O
7.769 | 0.009 | tNET | RR | 1 | R9C25[2][B] | main_tx_inst/serializer/ch_out_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C25[2][B] | main_tx_inst/serializer/ch_out_4_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C25[2][B] | main_tx_inst/serializer/ch_out_4_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.051, 40.710%; route: 2.529, 50.192%; tC2Q: 0.458, 9.097%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path11

Path Summary:

Slack | -1.369
Data Arrival Time | 7.769
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_12_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.808 | 1.508 | tNET | FF | 1 | R7C21[3][A] | main_tx_inst/serializer/n392_s13/I2
7.433 | 0.625 | tINS | FR | 1 | R7C21[3][A] | main_tx_inst/serializer/n392_s13/F
7.433 | 0.000 | tNET | RR | 1 | R7C21[3][A] | main_tx_inst/serializer/n392_s9/I0
7.583 | 0.150 | tINS | RR | 1 | R7C21[3][A] | main_tx_inst/serializer/n392_s9/O
7.583 | 0.000 | tNET | RR | 1 | R7C21[2][B] | main_tx_inst/serializer/n392_s5/I0
7.760 | 0.177 | tINS | RR | 1 | R7C21[2][B] | main_tx_inst/serializer/n392_s5/O
7.769 | 0.009 | tNET | RR | 1 | R7C21[2][B] | main_tx_inst/serializer/ch_out_12_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R7C21[2][B] | main_tx_inst/serializer/ch_out_12_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R7C21[2][B] | main_tx_inst/serializer/ch_out_12_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.051, 40.710%; route: 2.529, 50.192%; tC2Q: 0.458, 9.097%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path12

Path Summary:

Slack | -1.360
Data Arrival Time | 7.760
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_9_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.334 | 1.034 | tNET | FF | 1 | R11C22[3][A] | main_tx_inst/serializer/n395_s13/I2
7.433 | 1.099 | tINS | FF | 1 | R11C22[3][A] | main_tx_inst/serializer/n395_s13/F
7.433 | 0.000 | tNET | FF | 1 | R11C22[3][A] | main_tx_inst/serializer/n395_s9/I0
7.582 | 0.149 | tINS | FF | 1 | R11C22[3][A] | main_tx_inst/serializer/n395_s9/O
7.582 | 0.000 | tNET | FF | 1 | R11C22[2][B] | main_tx_inst/serializer/n395_s5/I0
7.745 | 0.163 | tINS | FF | 1 | R11C22[2][B] | main_tx_inst/serializer/n395_s5/O
7.760 | 0.015 | tNET | FF | 1 | R11C22[2][B] | main_tx_inst/serializer/ch_out_9_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C22[2][B] | main_tx_inst/serializer/ch_out_9_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C22[2][B] | main_tx_inst/serializer/ch_out_9_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.510, 49.911%; route: 2.061, 40.975%; tC2Q: 0.458, 9.114%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path13

Path Summary:

Slack | -1.300
Data Arrival Time | 7.701
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_21_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.339 | 1.039 | tNET | FF | 1 | R13C20[3][A] | main_tx_inst/serializer/n383_s13/I2
7.365 | 1.026 | tINS | FR | 1 | R13C20[3][A] | main_tx_inst/serializer/n383_s13/F
7.365 | 0.000 | tNET | RR | 1 | R13C20[3][A] | main_tx_inst/serializer/n383_s9/I0
7.515 | 0.150 | tINS | RR | 1 | R13C20[3][A] | main_tx_inst/serializer/n383_s9/O
7.515 | 0.000 | tNET | RR | 1 | R13C20[2][B] | main_tx_inst/serializer/n383_s5/I0
7.692 | 0.177 | tINS | RR | 1 | R13C20[2][B] | main_tx_inst/serializer/n383_s5/O
7.701 | 0.009 | tNET | RR | 1 | R13C20[2][B] | main_tx_inst/serializer/ch_out_21_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R13C20[2][B] | main_tx_inst/serializer/ch_out_21_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R13C20[2][B] | main_tx_inst/serializer/ch_out_21_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.452, 49.343%; route: 2.059, 41.434%; tC2Q: 0.458, 9.223%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path14

Path Summary:

Slack | -1.249
Data Arrival Time | 7.649
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_1_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/F
6.991 | 2.177 | tNET | FF | 1 | R12C17[3][A] | main_tx_inst/serializer/n403_s9/S0
7.463 | 0.472 | tINS | FR | 1 | R12C17[3][A] | main_tx_inst/serializer/n403_s9/O
7.463 | 0.000 | tNET | RR | 1 | R12C17[2][B] | main_tx_inst/serializer/n403_s5/I0
7.640 | 0.177 | tINS | RR | 1 | R12C17[2][B] | main_tx_inst/serializer/n403_s5/O
7.649 | 0.009 | tNET | RR | 1 | R12C17[2][B] | main_tx_inst/serializer/ch_out_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C17[2][B] | main_tx_inst/serializer/ch_out_1_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R12C17[2][B] | main_tx_inst/serializer/ch_out_1_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 25.926%; route: 3.185, 64.755%; tC2Q: 0.458, 9.320%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path15

Path Summary:

Slack | -1.249
Data Arrival Time | 7.649
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_5_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/F
6.991 | 2.177 | tNET | FF | 1 | R11C17[3][A] | main_tx_inst/serializer/n399_s9/S0
7.463 | 0.472 | tINS | FR | 1 | R11C17[3][A] | main_tx_inst/serializer/n399_s9/O
7.463 | 0.000 | tNET | RR | 1 | R11C17[2][B] | main_tx_inst/serializer/n399_s5/I0
7.640 | 0.177 | tINS | RR | 1 | R11C17[2][B] | main_tx_inst/serializer/n399_s5/O
7.649 | 0.009 | tNET | RR | 1 | R11C17[2][B] | main_tx_inst/serializer/ch_out_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C17[2][B] | main_tx_inst/serializer/ch_out_5_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C17[2][B] | main_tx_inst/serializer/ch_out_5_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 25.926%; route: 3.185, 64.755%; tC2Q: 0.458, 9.320%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path16

Path Summary:

Slack | -1.243
Data Arrival Time | 7.643
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_15_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.494 | 1.194 | tNET | FF | 1 | R9C22[3][A] | main_tx_inst/serializer/n389_s13/I2
7.316 | 0.822 | tINS | FF | 1 | R9C22[3][A] | main_tx_inst/serializer/n389_s13/F
7.316 | 0.000 | tNET | FF | 1 | R9C22[3][A] | main_tx_inst/serializer/n389_s9/I0
7.465 | 0.149 | tINS | FF | 1 | R9C22[3][A] | main_tx_inst/serializer/n389_s9/O
7.465 | 0.000 | tNET | FF | 1 | R9C22[2][B] | main_tx_inst/serializer/n389_s5/I0
7.628 | 0.163 | tINS | FF | 1 | R9C22[2][B] | main_tx_inst/serializer/n389_s5/O
7.643 | 0.015 | tNET | FF | 1 | R9C22[2][B] | main_tx_inst/serializer/ch_out_15_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C22[2][B] | main_tx_inst/serializer/ch_out_15_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C22[2][B] | main_tx_inst/serializer/ch_out_15_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 45.461%; route: 2.221, 45.208%; tC2Q: 0.458, 9.331%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path17

Path Summary:

Slack | -1.238
Data Arrival Time | 7.639
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_10_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.678 | 1.378 | tNET | FF | 1 | R8C17[3][A] | main_tx_inst/serializer/n394_s13/I2
7.303 | 0.625 | tINS | FR | 1 | R8C17[3][A] | main_tx_inst/serializer/n394_s13/F
7.303 | 0.000 | tNET | RR | 1 | R8C17[3][A] | main_tx_inst/serializer/n394_s9/I0
7.453 | 0.150 | tINS | RR | 1 | R8C17[3][A] | main_tx_inst/serializer/n394_s9/O
7.453 | 0.000 | tNET | RR | 1 | R8C17[2][B] | main_tx_inst/serializer/n394_s5/I0
7.630 | 0.177 | tINS | RR | 1 | R8C17[2][B] | main_tx_inst/serializer/n394_s5/O
7.639 | 0.009 | tNET | RR | 1 | R8C17[2][B] | main_tx_inst/serializer/ch_out_10_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R8C17[2][B] | main_tx_inst/serializer/ch_out_10_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R8C17[2][B] | main_tx_inst/serializer/ch_out_10_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.051, 41.794%; route: 2.398, 48.866%; tC2Q: 0.458, 9.340%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path18

Path Summary:

Slack | -1.220
Data Arrival Time | 7.621
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_8_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.660 | 1.360 | tNET | FF | 1 | R9C21[3][A] | main_tx_inst/serializer/n396_s13/I2
7.285 | 0.625 | tINS | FR | 1 | R9C21[3][A] | main_tx_inst/serializer/n396_s13/F
7.285 | 0.000 | tNET | RR | 1 | R9C21[3][A] | main_tx_inst/serializer/n396_s9/I0
7.435 | 0.150 | tINS | RR | 1 | R9C21[3][A] | main_tx_inst/serializer/n396_s9/O
7.435 | 0.000 | tNET | RR | 1 | R9C21[2][B] | main_tx_inst/serializer/n396_s5/I0
7.612 | 0.177 | tINS | RR | 1 | R9C21[2][B] | main_tx_inst/serializer/n396_s5/O
7.621 | 0.009 | tNET | RR | 1 | R9C21[2][B] | main_tx_inst/serializer/ch_out_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C21[2][B] | main_tx_inst/serializer/ch_out_8_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C21[2][B] | main_tx_inst/serializer/ch_out_8_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.051, 41.948%; route: 2.380, 48.677%; tC2Q: 0.458, 9.374%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path19

Path Summary:

Slack | -1.185
Data Arrival Time | 7.585
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_11_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.159 | 0.859 | tNET | FF | 1 | R8C18[3][A] | main_tx_inst/serializer/n393_s13/I2
7.258 | 1.099 | tINS | FF | 1 | R8C18[3][A] | main_tx_inst/serializer/n393_s13/F
7.258 | 0.000 | tNET | FF | 1 | R8C18[3][A] | main_tx_inst/serializer/n393_s9/I0
7.407 | 0.149 | tINS | FF | 1 | R8C18[3][A] | main_tx_inst/serializer/n393_s9/O
7.407 | 0.000 | tNET | FF | 1 | R8C18[2][B] | main_tx_inst/serializer/n393_s5/I0
7.570 | 0.163 | tINS | FF | 1 | R8C18[2][B] | main_tx_inst/serializer/n393_s5/O
7.585 | 0.015 | tNET | FF | 1 | R8C18[2][B] | main_tx_inst/serializer/ch_out_11_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R8C18[2][B] | main_tx_inst/serializer/ch_out_11_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R8C18[2][B] | main_tx_inst/serializer/ch_out_11_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.510, 51.709%; route: 1.886, 38.849%; tC2Q: 0.458, 9.442%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path20

Path Summary:

Slack | -1.147
Data Arrival Time | 7.547
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_7_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RR | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
3.633 | 0.444 | tNET | RR | 1 | R9C19[3][A] | main_tx_inst/serializer/n333_s5/I1
4.665 | 1.032 | tINS | RF | 24 | R9C19[3][A] | main_tx_inst/serializer/n333_s5/F
6.185 | 1.520 | tNET | FF | 1 | R11C24[3][B] | main_tx_inst/serializer/n397_s14/I2
7.211 | 1.026 | tINS | FR | 1 | R11C24[3][B] | main_tx_inst/serializer/n397_s14/F
7.211 | 0.000 | tNET | RR | 1 | R11C24[3][A] | main_tx_inst/serializer/n397_s9/I1
7.361 | 0.150 | tINS | RR | 1 | R11C24[3][A] | main_tx_inst/serializer/n397_s9/O
7.361 | 0.000 | tNET | RR | 1 | R11C24[2][B] | main_tx_inst/serializer/n397_s5/I0
7.538 | 0.177 | tINS | RR | 1 | R11C24[2][B] | main_tx_inst/serializer/n397_s5/O
7.547 | 0.009 | tNET | RR | 1 | R11C24[2][B] | main_tx_inst/serializer/ch_out_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C24[2][B] | main_tx_inst/serializer/ch_out_7_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C24[2][B] | main_tx_inst/serializer/ch_out_7_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.385, 49.523%; route: 1.973, 40.960%; tC2Q: 0.458, 9.517%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path21

Path Summary:

Slack | -1.134
Data Arrival Time | 11.546
Data Required Time | 10.411
From | main_rx_1_inst/transmitter/bit_counter_0_s3
To | main_rx_1_inst/transmitter/sdout_2_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.673 | 0.244 | tNET | RR | 1 | R7C40[0][A] | main_rx_1_inst/transmitter/bit_counter_0_s3/CLK
3.132 | 0.458 | tC2Q | RF | 101 | R7C40[0][A] | main_rx_1_inst/transmitter/bit_counter_0_s3/Q
5.337 | 2.205 | tNET | FF | 1 | R12C34[0][A] | main_rx_1_inst/transmitter/n1120_s80/I2
5.962 | 0.625 | tINS | FR | 1 | R12C34[0][A] | main_rx_1_inst/transmitter/n1120_s80/F
5.962 | 0.000 | tNET | RR | 1 | R12C34[0][A] | main_rx_1_inst/transmitter/n1120_s71/I0
6.112 | 0.150 | tINS | RR | 1 | R12C34[0][A] | main_rx_1_inst/transmitter/n1120_s71/O
6.112 | 0.000 | tNET | RR | 1 | R12C34[0][B] | main_rx_1_inst/transmitter/n1120_s69/I1
6.289 | 0.177 | tINS | RR | 1 | R12C34[0][B] | main_rx_1_inst/transmitter/n1120_s69/O
6.289 | 0.000 | tNET | RR | 1 | R12C34[1][B] | main_rx_1_inst/transmitter/n1120_s65/I1
6.466 | 0.177 | tINS | RR | 1 | R12C34[1][B] | main_rx_1_inst/transmitter/n1120_s65/O
6.891 | 0.426 | tNET | RR | 1 | R12C33[3][B] | main_rx_1_inst/transmitter/n1134_s2/I2
7.990 | 1.099 | tINS | RF | 1 | R12C33[3][B] | main_rx_1_inst/transmitter/n1134_s2/F
8.811 | 0.821 | tNET | FF | 1 | R12C35[3][B] | main_rx_1_inst/transmitter/n1134_s0/I1
9.437 | 0.626 | tINS | FF | 1 | R12C35[3][B] | main_rx_1_inst/transmitter/n1134_s0/F
11.546 | 2.108 | tNET | FF | 1 | IOR14[B] | main_rx_1_inst/transmitter/sdout_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
8.138 | 8.138 |  |  |  |  | active clock edge time
8.138 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
10.567 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
10.811 | 0.244 | tNET | RR | 1 | IOR14[B] | main_rx_1_inst/transmitter/sdout_2_s0/CLK
10.411 | -0.400 | tSu |  | 1 | IOR14[B] | main_rx_1_inst/transmitter/sdout_2_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 8.138
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.854, 32.167%; route: 5.560, 62.667%; tC2Q: 0.458, 5.166%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path22

Path Summary:

Slack | -1.083
Data Arrival Time | 7.483
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_2_s1
To | main_tx_inst/serializer/ch_out_18_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 31 | R9C20[1][B] | main_tx_inst/serializer/channel_cnt_2_s1/Q
4.201 | 1.011 | tNET | FF | 1 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/I2
5.300 | 1.099 | tINS | FF | 24 | R11C18[1][B] | main_tx_inst/serializer/n381_s11/F
6.334 | 1.034 | tNET | FF | 1 | R11C20[3][A] | main_tx_inst/serializer/n386_s13/I2
7.156 | 0.822 | tINS | FF | 1 | R11C20[3][A] | main_tx_inst/serializer/n386_s13/F
7.156 | 0.000 | tNET | FF | 1 | R11C20[3][A] | main_tx_inst/serializer/n386_s9/I0
7.305 | 0.149 | tINS | FF | 1 | R11C20[3][A] | main_tx_inst/serializer/n386_s9/O
7.305 | 0.000 | tNET | FF | 1 | R11C20[2][B] | main_tx_inst/serializer/n386_s5/I0
7.468 | 0.163 | tINS | FF | 1 | R11C20[2][B] | main_tx_inst/serializer/n386_s5/O
7.483 | 0.015 | tNET | FF | 1 | R11C20[2][B] | main_tx_inst/serializer/ch_out_18_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C20[2][B] | main_tx_inst/serializer/ch_out_18_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C20[2][B] | main_tx_inst/serializer/ch_out_18_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 46.992%; route: 2.061, 43.363%; tC2Q: 0.458, 9.645%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path23

Path Summary:

Slack | -1.060
Data Arrival Time | 7.460
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_14_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/F
6.802 | 1.988 | tNET | FF | 1 | R11C21[3][A] | main_tx_inst/serializer/n390_s9/S0
7.274 | 0.472 | tINS | FR | 1 | R11C21[3][A] | main_tx_inst/serializer/n390_s9/O
7.274 | 0.000 | tNET | RR | 1 | R11C21[2][B] | main_tx_inst/serializer/n390_s5/I0
7.451 | 0.177 | tINS | RR | 1 | R11C21[2][B] | main_tx_inst/serializer/n390_s5/O
7.460 | 0.009 | tNET | RR | 1 | R11C21[2][B] | main_tx_inst/serializer/ch_out_14_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C21[2][B] | main_tx_inst/serializer/ch_out_14_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C21[2][B] | main_tx_inst/serializer/ch_out_14_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 26.961%; route: 2.996, 63.347%; tC2Q: 0.458, 9.692%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path24

Path Summary:

Slack | -1.060
Data Arrival Time | 7.460
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_19_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 8 | R11C18[1][A] | main_tx_inst/serializer/channel_cnt_1_s3/Q
4.188 | 0.999 | tNET | FF | 1 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/I0
4.814 | 0.626 | tINS | FF | 24 | R9C20[2][B] | main_tx_inst/serializer/n381_s9/F
6.802 | 1.988 | tNET | FF | 1 | R11C19[3][A] | main_tx_inst/serializer/n385_s9/S0
7.274 | 0.472 | tINS | FR | 1 | R11C19[3][A] | main_tx_inst/serializer/n385_s9/O
7.274 | 0.000 | tNET | RR | 1 | R11C19[2][B] | main_tx_inst/serializer/n385_s5/I0
7.451 | 0.177 | tINS | RR | 1 | R11C19[2][B] | main_tx_inst/serializer/n385_s5/O
7.460 | 0.009 | tNET | RR | 1 | R11C19[2][B] | main_tx_inst/serializer/ch_out_19_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C19[2][B] | main_tx_inst/serializer/ch_out_19_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C19[2][B] | main_tx_inst/serializer/ch_out_19_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.275, 26.961%; route: 2.996, 63.347%; tC2Q: 0.458, 9.692%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path25

Path Summary:

Slack | -1.044
Data Arrival Time | 7.771
Data Required Time | 6.727
From | main_tx_inst/clocks/i2s_lrclk_s2
To | main_tx_inst/deserializer/sample_ch_4_l_buf_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
2.088 | 2.088 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
2.332 | 0.244 | tNET | RR | 1 | R22C26[2][A] | main_tx_inst/clocks/i2s_lrclk_s2/CLK
2.790 | 0.458 | tC2Q | RF | 6 | R22C26[2][A] | main_tx_inst/clocks/i2s_lrclk_s2/Q
3.949 | 1.159 | tNET | FF | 1 | R22C16[0][A] | main_tx_inst/deserializer/n2035_s0/I0
4.751 | 0.802 | tINS | FR | 96 | R22C16[0][A] | main_tx_inst/deserializer/n2035_s0/F
7.771 | 3.020 | tNET | RR | 1 | R17C15[1][B] | main_tx_inst/deserializer/sample_ch_4_l_buf_0_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R17C15[1][B] | main_tx_inst/deserializer/sample_ch_4_l_buf_0_s0/CLK
6.770 | -0.030 | tUnc |  |  |  | main_tx_inst/deserializer/sample_ch_4_l_buf_0_s0
6.727 | -0.043 | tSu |  | 1 | R17C15[1][B] | main_tx_inst/deserializer/sample_ch_4_l_buf_0_s0

Path Statistics:

Clock Skew | 0.399
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay | cell: 0.802, 14.745%; route: 4.179, 76.829%; tC2Q: 0.458, 8.426%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.142
Data Arrival Time | 2.844
Data Required Time | 2.702
From | main_tx_inst/clocks/aes_lrclk_s2
To | main_tx_inst/serializer/zaes_lrck_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/Q
2.844 | 0.934 | tNET | RR | 1 | R9C26[1][A] | main_tx_inst/serializer/zaes_lrck_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R9C26[1][A] | main_tx_inst/serializer/zaes_lrck_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst/serializer/zaes_lrck_s0
2.702 | 0.000 | tHld |  | 1 | R9C26[1][A] | main_tx_inst/serializer/zaes_lrck_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.934, 73.697%; tC2Q: 0.333, 26.303%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path2

Path Summary:

Slack | 0.558
Data Arrival Time | 1.254
Data Required Time | 0.696
From | main_rx_1_inst/clocks/bsync_pos_edge_s0
To | main_rx_1_inst/clocks/i2s_bclk_s2
Launch Clk | main_rx_1_inst/aes3_bclk:[R]
Latch Clk | main_rx_1_inst/aes3_bclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R8C29[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
0.683 | 0.683 | tNET | RR | 1 | R14C30[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0/CLK
1.016 | 0.333 | tC2Q | RR | 2 | R14C30[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0/Q
1.254 | 0.238 | tNET | RR | 1 | R14C30[2][A] | main_rx_1_inst/clocks/i2s_bclk_s2/SET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R8C29[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
0.683 | 0.683 | tNET | RR | 1 | R14C30[2][A] | main_rx_1_inst/clocks/i2s_bclk_s2/CLK
0.696 | 0.012 | tHld |  | 1 | R14C30[2][A] | main_rx_1_inst/clocks/i2s_bclk_s2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.683, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.683, 100.000%

### Path3

Path Summary:

Slack | 0.561
Data Arrival Time | 3.187
Data Required Time | 2.626
From | main_rx_1_inst/deserializer/bsync_pos_edge_s0
To | main_rx_1_inst/deserializer/channel_counter_0_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R22C37[1][A] | main_rx_1_inst/deserializer/bsync_pos_edge_s0/CLK
2.947 | 0.333 | tC2Q | RR | 12 | R22C37[1][A] | main_rx_1_inst/deserializer/bsync_pos_edge_s0/Q
3.187 | 0.240 | tNET | RR | 1 | R22C37[0][A] | main_rx_1_inst/deserializer/channel_counter_0_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R22C37[0][A] | main_rx_1_inst/deserializer/channel_counter_0_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R22C37[0][A] | main_rx_1_inst/deserializer/channel_counter_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path4

Path Summary:

Slack | 0.565
Data Arrival Time | 3.191
Data Required Time | 2.626
From | main_rx_1_inst/clocks/zzaes_lrclk_s0
To | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R21C28[1][B] | main_rx_1_inst/clocks/zzaes_lrclk_s0/CLK
2.947 | 0.333 | tC2Q | RR | 3 | R21C28[1][B] | main_rx_1_inst/clocks/zzaes_lrclk_s0/Q
3.191 | 0.244 | tNET | RR | 1 | R21C28[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R21C28[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R21C28[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.244, 42.242%; tC2Q: 0.333, 57.758%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path5

Path Summary:

Slack | 0.568
Data Arrival Time | 3.195
Data Required Time | 2.626
From | main_rx_1_inst/receiver/aes3_clk_s0
To | main_rx_1_inst/receiver/sync_cnt_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R9C30[0][B] | main_rx_1_inst/receiver/aes3_clk_s0/CLK
2.947 | 0.333 | tC2Q | RR | 18 | R9C30[0][B] | main_rx_1_inst/receiver/aes3_clk_s0/Q
3.195 | 0.247 | tNET | RR | 1 | R9C30[1][A] | main_rx_1_inst/receiver/sync_cnt_4_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R9C30[1][A] | main_rx_1_inst/receiver/sync_cnt_4_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R9C30[1][A] | main_rx_1_inst/receiver/sync_cnt_4_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.247, 42.594%; tC2Q: 0.333, 57.406%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path6

Path Summary:

Slack | 0.587
Data Arrival Time | 1.283
Data Required Time | 0.696
From | main_rx_1_inst/clocks/zzbsync_s0
To | main_rx_1_inst/clocks/bsync_pos_edge_s0
Launch Clk | main_rx_1_inst/aes3_bclk:[R]
Latch Clk | main_rx_1_inst/aes3_bclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R8C29[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
0.683 | 0.683 | tNET | RR | 1 | R14C29[0][B] | main_rx_1_inst/clocks/zzbsync_s0/CLK
1.016 | 0.333 | tC2Q | RR | 2 | R14C29[0][B] | main_rx_1_inst/clocks/zzbsync_s0/Q
1.283 | 0.266 | tNET | RR | 1 | R14C30[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R8C29[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
0.683 | 0.683 | tNET | RR | 1 | R14C30[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0/CLK
0.696 | 0.012 | tHld |  | 1 | R14C30[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.683, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 44.393%; tC2Q: 0.333, 55.607%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.683, 100.000%

### Path7

Path Summary:

Slack | 0.594
Data Arrival Time | 3.221
Data Required Time | 2.626
From | main_rx_1_inst/receiver/aes3_clk_s0
To | main_rx_1_inst/receiver/sync_cnt_2_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R9C30[0][B] | main_rx_1_inst/receiver/aes3_clk_s0/CLK
2.947 | 0.333 | tC2Q | RR | 18 | R9C30[0][B] | main_rx_1_inst/receiver/aes3_clk_s0/Q
3.221 | 0.273 | tNET | RR | 1 | R9C29[2][A] | main_rx_1_inst/receiver/sync_cnt_2_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R9C29[2][A] | main_rx_1_inst/receiver/sync_cnt_2_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R9C29[2][A] | main_rx_1_inst/receiver/sync_cnt_2_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.273, 45.061%; tC2Q: 0.333, 54.939%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path8

Path Summary:

Slack | 0.594
Data Arrival Time | 3.221
Data Required Time | 2.626
From | main_rx_1_inst/receiver/aes3_clk_s0
To | main_rx_1_inst/receiver/sync_cnt_3_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R9C30[0][B] | main_rx_1_inst/receiver/aes3_clk_s0/CLK
2.947 | 0.333 | tC2Q | RR | 18 | R9C30[0][B] | main_rx_1_inst/receiver/aes3_clk_s0/Q
3.221 | 0.273 | tNET | RR | 1 | R9C29[1][B] | main_rx_1_inst/receiver/sync_cnt_3_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R9C29[1][B] | main_rx_1_inst/receiver/sync_cnt_3_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R9C29[1][B] | main_rx_1_inst/receiver/sync_cnt_3_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.273, 45.061%; tC2Q: 0.333, 54.939%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path9

Path Summary:

Slack | 0.671
Data Arrival Time | 3.373
Data Required Time | 2.702
From | main_tx_inst/clocks/i2s_bclk_s2
To | main_tx_inst/deserializer/zbclk_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R18C26[2][B] | main_tx_inst/clocks/i2s_bclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R18C26[2][B] | main_tx_inst/clocks/i2s_bclk_s2/Q
3.373 | 1.463 | tNET | RR | 1 | R22C19[0][B] | main_tx_inst/deserializer/zbclk_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C19[0][B] | main_tx_inst/deserializer/zbclk_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst/deserializer/zbclk_s0
2.702 | 0.000 | tHld |  | 1 | R22C19[0][B] | main_tx_inst/deserializer/zbclk_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.463, 81.440%; tC2Q: 0.333, 18.560%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path10

Path Summary:

Slack | 0.708
Data Arrival Time | 3.380
Data Required Time | 2.672
From | main_tx_inst/deserializer/lrck_neg_edge_s4
To | main_tx_inst/deserializer/lrck_neg_edge_s4
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R18C21[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/CLK
3.005 | 0.333 | tC2Q | RR | 2 | R18C21[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/Q
3.008 | 0.002 | tNET | RR | 1 | R18C21[0][A] | main_tx_inst/deserializer/n30_s2/I0
3.380 | 0.372 | tINS | RF | 1 | R18C21[0][A] | main_tx_inst/deserializer/n30_s2/F
3.380 | 0.000 | tNET | FF | 1 | R18C21[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 631 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R18C21[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/CLK
2.672 | 0.000 | tHld |  | 1 | R18C21[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path11

Path Summary:

Slack | 0.708
Data Arrival Time | 3.322
Data Required Time | 2.614
From | main_rx_1_inst/transmitter/bit_counter_1_s3
To | main_rx_1_inst/transmitter/bit_counter_1_s3
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R7C33[0][A] | main_rx_1_inst/transmitter/bit_counter_1_s3/CLK
2.947 | 0.333 | tC2Q | RR | 52 | R7C33[0][A] | main_rx_1_inst/transmitter/bit_counter_1_s3/Q
2.950 | 0.002 | tNET | RR | 1 | R7C33[0][A] | main_rx_1_inst/transmitter/n30_s3/I2
3.322 | 0.372 | tINS | RF | 1 | R7C33[0][A] | main_rx_1_inst/transmitter/n30_s3/F
3.322 | 0.000 | tNET | FF | 1 | R7C33[0][A] | main_rx_1_inst/transmitter/bit_counter_1_s3/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R7C33[0][A] | main_rx_1_inst/transmitter/bit_counter_1_s3/CLK
2.614 | 0.000 | tHld |  | 1 | R7C33[0][A] | main_rx_1_inst/transmitter/bit_counter_1_s3

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path12

Path Summary:

Slack | 0.708
Data Arrival Time | 3.322
Data Required Time | 2.614
From | main_rx_1_inst/transmitter/bclk_neg_edge_s4
To | main_rx_1_inst/transmitter/bclk_neg_edge_s4
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R14C41[0][A] | main_rx_1_inst/transmitter/bclk_neg_edge_s4/CLK
2.947 | 0.333 | tC2Q | RR | 5 | R14C41[0][A] | main_rx_1_inst/transmitter/bclk_neg_edge_s4/Q
2.950 | 0.002 | tNET | RR | 1 | R14C41[0][A] | main_rx_1_inst/transmitter/n8_s2/I0
3.322 | 0.372 | tINS | RF | 1 | R14C41[0][A] | main_rx_1_inst/transmitter/n8_s2/F
3.322 | 0.000 | tNET | FF | 1 | R14C41[0][A] | main_rx_1_inst/transmitter/bclk_neg_edge_s4/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R14C41[0][A] | main_rx_1_inst/transmitter/bclk_neg_edge_s4/CLK
2.614 | 0.000 | tHld |  | 1 | R14C41[0][A] | main_rx_1_inst/transmitter/bclk_neg_edge_s4

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path13

Path Summary:

Slack | 0.708
Data Arrival Time | 3.322
Data Required Time | 2.614
From | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0
To | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R20C28[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0/CLK
2.947 | 0.333 | tC2Q | RR | 3 | R20C28[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0/Q
2.950 | 0.002 | tNET | RR | 1 | R20C28[0][A] | main_rx_1_inst/clocks/n229_s2/I2
3.322 | 0.372 | tINS | RF | 1 | R20C28[0][A] | main_rx_1_inst/clocks/n229_s2/F
3.322 | 0.000 | tNET | FF | 1 | R20C28[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R20C28[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0/CLK
2.614 | 0.000 | tHld |  | 1 | R20C28[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_7_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path14

Path Summary:

Slack | 0.708
Data Arrival Time | 3.322
Data Required Time | 2.614
From | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0
To | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R20C30[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0/CLK
2.947 | 0.333 | tC2Q | RR | 3 | R20C30[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0/Q
2.950 | 0.002 | tNET | RR | 1 | R20C30[0][A] | main_rx_1_inst/clocks/n206_s2/I3
3.322 | 0.372 | tINS | RF | 1 | R20C30[0][A] | main_rx_1_inst/clocks/n206_s2/F
3.322 | 0.000 | tNET | FF | 1 | R20C30[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R20C30[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0/CLK
2.614 | 0.000 | tHld |  | 1 | R20C30[0][A] | main_rx_1_inst/clocks/count_i2s_lrclk_30_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path15

Path Summary:

Slack | 0.708
Data Arrival Time | 3.322
Data Required Time | 2.614
From | main_rx_1_inst/receiver/reg_clk_period_0_s0
To | main_rx_1_inst/receiver/reg_clk_period_0_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R12C29[0][A] | main_rx_1_inst/receiver/reg_clk_period_0_s0/CLK
2.947 | 0.333 | tC2Q | RR | 3 | R12C29[0][A] | main_rx_1_inst/receiver/reg_clk_period_0_s0/Q
2.950 | 0.002 | tNET | RR | 1 | R12C29[0][A] | main_rx_1_inst/receiver/n79_s2/I0
3.322 | 0.372 | tINS | RF | 1 | R12C29[0][A] | main_rx_1_inst/receiver/n79_s2/F
3.322 | 0.000 | tNET | FF | 1 | R12C29[0][A] | main_rx_1_inst/receiver/reg_clk_period_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R12C29[0][A] | main_rx_1_inst/receiver/reg_clk_period_0_s0/CLK
2.614 | 0.000 | tHld |  | 1 | R12C29[0][A] | main_rx_1_inst/receiver/reg_clk_period_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path16

Path Summary:

Slack | 0.708
Data Arrival Time | 3.322
Data Required Time | 2.614
From | main_rx_1_inst/receiver/sync_cnt_5_s0
To | main_rx_1_inst/receiver/sync_cnt_5_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R11C29[1][A] | main_rx_1_inst/receiver/sync_cnt_5_s0/CLK
2.947 | 0.333 | tC2Q | RR | 2 | R11C29[1][A] | main_rx_1_inst/receiver/sync_cnt_5_s0/Q
2.950 | 0.002 | tNET | RR | 1 | R11C29[1][A] | main_rx_1_inst/receiver/n22_s2/I3
3.322 | 0.372 | tINS | RF | 1 | R11C29[1][A] | main_rx_1_inst/receiver/n22_s2/F
3.322 | 0.000 | tNET | FF | 1 | R11C29[1][A] | main_rx_1_inst/receiver/sync_cnt_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R11C29[1][A] | main_rx_1_inst/receiver/sync_cnt_5_s0/CLK
2.614 | 0.000 | tHld |  | 1 | R11C29[1][A] | main_rx_1_inst/receiver/sync_cnt_5_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path17

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/transmitter/data_biphase_s1
To | main_tx_inst2/transmitter/data_biphase_s1
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R21C8[0][A] | main_tx_inst2/transmitter/data_biphase_s1/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R21C8[0][A] | main_tx_inst2/transmitter/data_biphase_s1/Q
1.912 | 0.002 | tNET | RR | 1 | R21C8[0][A] | main_tx_inst2/transmitter/n2535_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R21C8[0][A] | main_tx_inst2/transmitter/n2535_s2/F
2.284 | 0.000 | tNET | FF | 1 | R21C8[0][A] | main_tx_inst2/transmitter/data_biphase_s1/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R21C8[0][A] | main_tx_inst2/transmitter/data_biphase_s1/CLK
1.577 | 0.000 | tHld |  | 1 | R21C8[0][A] | main_tx_inst2/transmitter/data_biphase_s1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path18

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst/clocks/aes_lrclk_s2
To | main_tx_inst/clocks/aes_lrclk_s2
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/Q
1.912 | 0.002 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/clocks/n264_s3/I0
2.284 | 0.372 | tINS | RF | 1 | R16C26[1][A] | main_tx_inst/clocks/n264_s3/F
2.284 | 0.000 | tNET | FF | 1 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/CLK
1.577 | 0.000 | tHld |  | 1 | R16C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path19

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst/clocks/count_aes_lrclk_0_s0
To | main_tx_inst/clocks/count_aes_lrclk_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R16C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R16C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/Q
1.912 | 0.002 | tNET | RR | 1 | R16C25[0][A] | main_tx_inst/clocks/n255_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R16C25[0][A] | main_tx_inst/clocks/n255_s2/F
2.284 | 0.000 | tNET | FF | 1 | R16C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R16C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R16C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path20

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst/clocks/count_i2s_lrclk_0_s0
To | main_tx_inst/clocks/count_i2s_lrclk_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R22C26[1][A] | main_tx_inst/clocks/count_i2s_lrclk_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R22C26[1][A] | main_tx_inst/clocks/count_i2s_lrclk_0_s0/Q
1.912 | 0.002 | tNET | RR | 1 | R22C26[1][A] | main_tx_inst/clocks/n143_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R22C26[1][A] | main_tx_inst/clocks/n143_s2/F
2.284 | 0.000 | tNET | FF | 1 | R22C26[1][A] | main_tx_inst/clocks/count_i2s_lrclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R22C26[1][A] | main_tx_inst/clocks/count_i2s_lrclk_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R22C26[1][A] | main_tx_inst/clocks/count_i2s_lrclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path21

Path Summary:

Slack | 0.708
Data Arrival Time | 1.391
Data Required Time | 0.683
From | main_rx_1_inst/clocks/count_i2s_bclk_0_s0
To | main_rx_1_inst/clocks/count_i2s_bclk_0_s0
Launch Clk | main_rx_1_inst/aes3_bclk:[R]
Latch Clk | main_rx_1_inst/aes3_bclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R8C29[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
0.683 | 0.683 | tNET | RR | 1 | R14C29[1][A] | main_rx_1_inst/clocks/count_i2s_bclk_0_s0/CLK
1.016 | 0.333 | tC2Q | RR | 3 | R14C29[1][A] | main_rx_1_inst/clocks/count_i2s_bclk_0_s0/Q
1.019 | 0.002 | tNET | RR | 1 | R14C29[1][A] | main_rx_1_inst/clocks/n62_s2/I0
1.391 | 0.372 | tINS | RF | 1 | R14C29[1][A] | main_rx_1_inst/clocks/n62_s2/F
1.391 | 0.000 | tNET | FF | 1 | R14C29[1][A] | main_rx_1_inst/clocks/count_i2s_bclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R8C29[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
0.683 | 0.683 | tNET | RR | 1 | R14C29[1][A] | main_rx_1_inst/clocks/count_i2s_bclk_0_s0/CLK
0.683 | 0.000 | tHld |  | 1 | R14C29[1][A] | main_rx_1_inst/clocks/count_i2s_bclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.683, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.683, 100.000%

### Path22

Path Summary:

Slack | 0.709
Data Arrival Time | 2.285
Data Required Time | 1.577
From | main_tx_inst2/transmitter/frame_counter_0_s0
To | main_tx_inst2/transmitter/frame_counter_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R20C8[1][A] | main_tx_inst2/transmitter/frame_counter_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 4 | R20C8[1][A] | main_tx_inst2/transmitter/frame_counter_0_s0/Q
1.913 | 0.004 | tNET | RR | 1 | R20C8[1][A] | main_tx_inst2/transmitter/n95_s2/I0
2.285 | 0.372 | tINS | RF | 1 | R20C8[1][A] | main_tx_inst2/transmitter/n95_s2/F
2.285 | 0.000 | tNET | FF | 1 | R20C8[1][A] | main_tx_inst2/transmitter/frame_counter_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R20C8[1][A] | main_tx_inst2/transmitter/frame_counter_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R20C8[1][A] | main_tx_inst2/transmitter/frame_counter_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path23

Path Summary:

Slack | 0.709
Data Arrival Time | 2.285
Data Required Time | 1.577
From | main_tx_inst/transmitter/data_biphase_s1
To | main_tx_inst/transmitter/data_biphase_s1
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R14C10[1][A] | main_tx_inst/transmitter/data_biphase_s1/CLK
1.910 | 0.333 | tC2Q | RR | 4 | R14C10[1][A] | main_tx_inst/transmitter/data_biphase_s1/Q
1.913 | 0.004 | tNET | RR | 1 | R14C10[1][A] | main_tx_inst/transmitter/n2535_s2/I0
2.285 | 0.372 | tINS | RF | 1 | R14C10[1][A] | main_tx_inst/transmitter/n2535_s2/F
2.285 | 0.000 | tNET | FF | 1 | R14C10[1][A] | main_tx_inst/transmitter/data_biphase_s1/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R14C10[1][A] | main_tx_inst/transmitter/data_biphase_s1/CLK
1.577 | 0.000 | tHld |  | 1 | R14C10[1][A] | main_tx_inst/transmitter/data_biphase_s1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path24

Path Summary:

Slack | 0.709
Data Arrival Time | 2.285
Data Required Time | 1.577
From | main_tx_inst/transmitter/frame_counter_0_s0
To | main_tx_inst/transmitter/frame_counter_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R13C8[0][A] | main_tx_inst/transmitter/frame_counter_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 5 | R13C8[0][A] | main_tx_inst/transmitter/frame_counter_0_s0/Q
1.913 | 0.004 | tNET | RR | 1 | R13C8[0][A] | main_tx_inst/transmitter/n95_s2/I0
2.285 | 0.372 | tINS | RF | 1 | R13C8[0][A] | main_tx_inst/transmitter/n95_s2/F
2.285 | 0.000 | tNET | FF | 1 | R13C8[0][A] | main_tx_inst/transmitter/frame_counter_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R13C8[0][A] | main_tx_inst/transmitter/frame_counter_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R13C8[0][A] | main_tx_inst/transmitter/frame_counter_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path25

Path Summary:

Slack | 0.709
Data Arrival Time | 2.285
Data Required Time | 1.577
From | main_tx_inst/transmitter/bit_counter_0_s0
To | main_tx_inst/transmitter/bit_counter_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R21C7[0][A] | main_tx_inst/transmitter/bit_counter_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 9 | R21C7[0][A] | main_tx_inst/transmitter/bit_counter_0_s0/Q
1.913 | 0.004 | tNET | RR | 1 | R21C7[0][A] | main_tx_inst2/transmitter/n10_s2/I0
2.285 | 0.372 | tINS | RF | 1 | R21C7[0][A] | main_tx_inst2/transmitter/n10_s2/F
2.285 | 0.000 | tNET | FF | 1 | R21C7[0][A] | main_tx_inst/transmitter/bit_counter_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 329 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R21C7[0][A] | main_tx_inst/transmitter/bit_counter_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R21C7[0][A] | main_tx_inst/transmitter/bit_counter_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/zzbsync_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/zzbsync_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/zzbsync_s0/CLK

### MPW2

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_2_r_6_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_2_r_6_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_2_r_6_s0/CLK

### MPW3

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_1_l_14_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_1_l_14_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_1_l_14_s0/CLK

### MPW4

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_2_l_6_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_2_l_6_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_2_l_6_s0/CLK

### MPW5

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_l_14_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_l_14_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_l_14_s0/CLK

### MPW6

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_l_6_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_l_6_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_l_6_s0/CLK

### MPW7

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_l_2_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_l_2_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_l_2_s0/CLK

### MPW8

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_l_0_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_l_0_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_l_0_s0/CLK

### MPW9

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_4_l_23_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_4_l_23_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_4_l_23_s0/CLK

### MPW10

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_l_1_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_l_1_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_l_1_s0/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
631 | clock_200M | -1.527 | 0.262
531 | clock_100M | -1.458 | 0.262
329 | i2s_in_sclk_d | -1.044 | 0.262
195 | new_data_pos_edge | -0.048 | 2.179
195 | n175_10_4 | 27.686 | 3.462
192 | n1680_3 | 0.368 | 2.298
101 | bit_counter[0] | -1.458 | 2.329
96 | n1658_4 | -0.152 | 2.462
96 | n2035_3 | -1.044 | 3.426
96 | n1844_4 | -0.512 | 2.462

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R9C19 | 84.72%
R17C37 | 84.72%
R11C37 | 83.33%
R18C28 | 83.33%
R12C14 | 83.33%
R17C33 | 83.33%
R15C39 | 83.33%
R12C35 | 81.94%
R18C30 | 81.94%
R9C34 | 81.94%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---