
module main_rx (
    input clk,
    input reset_n, 

    input  aes3_rx,
    
    output i2s_out_bclk,
    output i2s_out_lrck,
    output i2s_out_data_1,
    output i2s_out_data_2,
    output i2s_out_data_3,
    output i2s_out_data_4,

    output locked
);


wire aes3_bclk;
wire aes3_lrck;
wire aes3_sdata;
wire aes3_bsync;

aes3rx receiver(
	.clk(clk),
	.reset(!reset_n),

	.aes3(aes3_rx),

	.sclk(aes3_bclk),
	.lrck(aes3_lrck),
	.sdata(aes3_sdata),
	.bsync(aes3_bsync),
	.active(locked)
);

wire i2s_bclk;
wire i2s_lrck;
wire i2s_lrclk_delayed;
ultranet_rx_clocks clocks(
	.clk(clk),

	.bsync(aes3_bsync),

	.aes_bclk(aes3_bclk),
	.aes_lrclk(aes3_lrck),

	.i2s_bclk(i2s_bclk),
	.i2s_lrclk(i2s_lrck)
);



wire [23:0] audio_sample;
wire [2:0] audio_channel;
wire aes3_new_data;

ultranet_rx_deserializer deserializer(
	.clk(clk),

	.bsync(aes3_bsync),

	.bclk(aes3_bclk),
	.sdata(aes3_sdata),
	.lrclk(aes3_lrck),

	.sample_out(audio_sample),
	.channel(audio_channel),
	.new_data(aes3_new_data)
);



wire [23:0] audio_sample_1;
wire [23:0] audio_sample_2;
wire [23:0] audio_sample_3;
wire [23:0] audio_sample_4;
wire [23:0] audio_sample_5;
wire [23:0] audio_sample_6;
wire [23:0] audio_sample_7;
wire [23:0] audio_sample_8;

ultranet_rx_demux demuxer(
	.clk(clk),

	.sample_in(audio_sample),
	.channel(audio_channel),
	.new_data(aes3_new_data),
		
	.ch1_out(audio_sample_1),
	.ch2_out(audio_sample_2),
	.ch3_out(audio_sample_3),
	.ch4_out(audio_sample_4),
	.ch5_out(audio_sample_5),
	.ch6_out(audio_sample_6),
	.ch7_out(audio_sample_7),
	.ch8_out(audio_sample_8)
);


i2s_quad_transmitter transmitter(
	.clk(clk),
	.reset_n(reset_n),
    
	.bclk(i2s_bclk),
	.lrclk(i2s_lrck),

	.sample_ch_1_l({ audio_sample_1, 8'b00000000}),
	.sample_ch_1_r({ audio_sample_2, 8'b00000000}),
	.sample_ch_2_l({ audio_sample_3, 8'b00000000}),
	.sample_ch_2_r({ audio_sample_4, 8'b00000000}),
	.sample_ch_3_l({ audio_sample_5, 8'b00000000}),
	.sample_ch_3_r({ audio_sample_6, 8'b00000000}),
	.sample_ch_4_l({ audio_sample_7, 8'b00000000}),
	.sample_ch_4_r({ audio_sample_8, 8'b00000000}),

	.sdout_1(i2s_out_data_1),
	.sdout_2(i2s_out_data_2),
	.sdout_3(i2s_out_data_3),
	.sdout_4(i2s_out_data_4)
);

assign i2s_out_bclk = i2s_bclk;
assign i2s_out_lrck = i2s_lrck;

endmodule