- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report

Design File

C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd

GowinSynthesis Constraints File | ---
Tool Version | V1.9.10.03 Education (64-bit)
Part Number | GW1NR-LV9QN88PC6/I5
Device | GW1NR-9
Device Version | C
Created Time | Tue Mar 18 23:31:35 2025
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | top

Synthesis Process

Running parser:
CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.459s, Peak memory usage = 337.070MB
Running netlist conversion:
CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
Optimizing Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.412s, Peak memory usage = 337.070MB
Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 337.070MB
Optimizing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.368s, Peak memory usage = 337.070MB
Running inference:
Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 337.070MB
Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 337.070MB
Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 337.070MB
Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 337.070MB
Running technical mapping:
Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 337.070MB
Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 337.070MB
Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 337.070MB
Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 337.070MB
Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 337.070MB
Generate output files:
CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 337.070MB

Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 337.070MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 37
I/O Buf | 31
IBUF | 8
OBUF | 21
TBUF | 2
Register | 1527
DFF | 63
DFFE | 1039
DFFS | 2
DFFSE | 32
DFFR | 165
DFFRE | 226
LUT | 498
LUT2 | 48
LUT3 | 283
LUT4 | 167
ALU | 150
ALU | 150
INV | 27
INV | 27
CLOCK | 1
rPLL | 1

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 675(525 LUT, 150 ALU) / 8640 | 8%
Register | 1527 / 6693 | 23%
--Register as Latch | 0 / 6693 | 0%
--Register as FF | 1527 / 6693 | 23%
BSRAM | 0 / 26 | 0%

# Timing

## Clock Summary:

NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
1 | i2s_in_sclk | Base | 40.690 | 24.6 | 0.000 | 20.345 |  |  | i2s_in_sclk_ibuf/I
2 | main_rx_1_inst/receiver/aes3_bclk | Base | 20.000 | 50.0 | 0.000 | 10.000 |  |  | main_rx_1_inst/receiver/sclk_s0/Q
3 | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Generated | 4.069 | 245.8 | 0.000 | 2.035 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUT
4 | pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Generated | 4.069 | 245.8 | 0.000 | 2.035 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTP
5 | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Generated | 8.138 | 122.9 | 0.000 | 4.069 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTD
6 | pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 12.207 | 81.9 | 0.000 | 6.104 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTD3

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | i2s_in_sclk | 24.576(MHz) | 85.724(MHz) | 5 | TOP
2 | main_rx_1_inst/receiver/aes3_bclk | 50.000(MHz) | 125.073(MHz) | 4 | TOP
3 | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | 245.760(MHz) | 126.721(MHz) | 3 | TOP
4 | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | 122.880(MHz) | 90.307(MHz) | 5 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | -3.822
Data Arrival Time | 9.373
Data Required Time | 5.551
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_0_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
1.156 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
1.882 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/channel_cnt_1_s3/CLK
2.340 | 0.458 | tC2Q | RF | 8 | main_tx_inst/serializer/channel_cnt_1_s3/Q
3.300 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n237_s2/I1
4.399 | 1.099 | tINS | FF | 24 | main_tx_inst/serializer/n237_s2/F
5.359 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n404_s12/I2
6.181 | 0.822 | tINS | FF | 1 | main_tx_inst/serializer/n404_s12/F
7.141 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n404_s10/I1
7.290 | 0.149 | tINS | FF | 1 | main_tx_inst/serializer/n404_s10/O
8.250 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n404_s5/I1
8.413 | 0.163 | tINS | FF | 1 | main_tx_inst/serializer/n404_s5/O
9.373 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/ch_out_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
4.069 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
5.225 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
5.951 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/ch_out_0_s0/CLK
5.551 | -0.400 | tSu |  | 1 | main_tx_inst/serializer/ch_out_0_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 4.069
Logic Level: | 3
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: | cell: 2.233, 29.808%; route: 4.800, 64.074%; tC2Q: 0.458, 6.118%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%

### Path 2

Path Summary:

Slack | -3.822
Data Arrival Time | 9.373
Data Required Time | 5.551
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_1_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
1.156 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
1.882 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/channel_cnt_1_s3/CLK
2.340 | 0.458 | tC2Q | RF | 8 | main_tx_inst/serializer/channel_cnt_1_s3/Q
3.300 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n237_s2/I1
4.399 | 1.099 | tINS | FF | 24 | main_tx_inst/serializer/n237_s2/F
5.359 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n403_s12/I2
6.181 | 0.822 | tINS | FF | 1 | main_tx_inst/serializer/n403_s12/F
7.141 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n403_s10/I1
7.290 | 0.149 | tINS | FF | 1 | main_tx_inst/serializer/n403_s10/O
8.250 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n403_s5/I1
8.413 | 0.163 | tINS | FF | 1 | main_tx_inst/serializer/n403_s5/O
9.373 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/ch_out_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
4.069 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
5.225 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
5.951 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/ch_out_1_s0/CLK
5.551 | -0.400 | tSu |  | 1 | main_tx_inst/serializer/ch_out_1_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 4.069
Logic Level: | 3
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: | cell: 2.233, 29.808%; route: 4.800, 64.074%; tC2Q: 0.458, 6.118%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%

### Path 3

Path Summary:

Slack | -3.822
Data Arrival Time | 9.373
Data Required Time | 5.551
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_2_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
1.156 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
1.882 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/channel_cnt_1_s3/CLK
2.340 | 0.458 | tC2Q | RF | 8 | main_tx_inst/serializer/channel_cnt_1_s3/Q
3.300 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n237_s2/I1
4.399 | 1.099 | tINS | FF | 24 | main_tx_inst/serializer/n237_s2/F
5.359 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n402_s12/I2
6.181 | 0.822 | tINS | FF | 1 | main_tx_inst/serializer/n402_s12/F
7.141 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n402_s10/I1
7.290 | 0.149 | tINS | FF | 1 | main_tx_inst/serializer/n402_s10/O
8.250 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n402_s5/I1
8.413 | 0.163 | tINS | FF | 1 | main_tx_inst/serializer/n402_s5/O
9.373 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/ch_out_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
4.069 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
5.225 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
5.951 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/ch_out_2_s0/CLK
5.551 | -0.400 | tSu |  | 1 | main_tx_inst/serializer/ch_out_2_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 4.069
Logic Level: | 3
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: | cell: 2.233, 29.808%; route: 4.800, 64.074%; tC2Q: 0.458, 6.118%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%

### Path 4

Path Summary:

Slack | -3.822
Data Arrival Time | 9.373
Data Required Time | 5.551
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_3_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
1.156 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
1.882 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/channel_cnt_1_s3/CLK
2.340 | 0.458 | tC2Q | RF | 8 | main_tx_inst/serializer/channel_cnt_1_s3/Q
3.300 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n237_s2/I1
4.399 | 1.099 | tINS | FF | 24 | main_tx_inst/serializer/n237_s2/F
5.359 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n401_s12/I2
6.181 | 0.822 | tINS | FF | 1 | main_tx_inst/serializer/n401_s12/F
7.141 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n401_s10/I1
7.290 | 0.149 | tINS | FF | 1 | main_tx_inst/serializer/n401_s10/O
8.250 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n401_s5/I1
8.413 | 0.163 | tINS | FF | 1 | main_tx_inst/serializer/n401_s5/O
9.373 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/ch_out_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
4.069 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
5.225 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
5.951 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/ch_out_3_s0/CLK
5.551 | -0.400 | tSu |  | 1 | main_tx_inst/serializer/ch_out_3_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 4.069
Logic Level: | 3
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: | cell: 2.233, 29.808%; route: 4.800, 64.074%; tC2Q: 0.458, 6.118%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%

### Path 5

Path Summary:

Slack | -3.822
Data Arrival Time | 9.373
Data Required Time | 5.551
From | main_tx_inst/serializer/channel_cnt_1_s3
To | main_tx_inst/serializer/ch_out_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
1.156 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
1.882 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/channel_cnt_1_s3/CLK
2.340 | 0.458 | tC2Q | RF | 8 | main_tx_inst/serializer/channel_cnt_1_s3/Q
3.300 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n237_s2/I1
4.399 | 1.099 | tINS | FF | 24 | main_tx_inst/serializer/n237_s2/F
5.359 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n400_s12/I2
6.181 | 0.822 | tINS | FF | 1 | main_tx_inst/serializer/n400_s12/F
7.141 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n400_s10/I1
7.290 | 0.149 | tINS | FF | 1 | main_tx_inst/serializer/n400_s10/O
8.250 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/n400_s5/I1
8.413 | 0.163 | tINS | FF | 1 | main_tx_inst/serializer/n400_s5/O
9.373 | 0.960 | tNET | FF | 1 | main_tx_inst/serializer/ch_out_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
4.069 | 0.000 |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
5.225 | 1.156 | tCL | RR | 631 | pll_main_clock/rpll_inst/CLKOUT
5.951 | 0.726 | tNET | RR | 1 | main_tx_inst/serializer/ch_out_4_s0/CLK
5.551 | -0.400 | tSu |  | 1 | main_tx_inst/serializer/ch_out_4_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 4.069
Logic Level: | 3
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: | cell: 2.233, 29.808%; route: 4.800, 64.074%; tC2Q: 0.458, 6.118%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000%