
module main_tx (

    input clk,                     // 100Mhz
    input reset_n, 

    input i2s_in_sclk,
    output i2s_in_bclk,
    output i2s_in_lrclk,
    input i2s_in_data_1,
    input i2s_in_data_2,
    input i2s_in_data_3,
    input i2s_in_data_4,
        
    output aes3_tx,

    output bsync,

    output debug_3,
    output debug_4,

	input	[383:0] channel_status,
	input	[383:0] user_status,
	input	valid
);

wire aes_bclk;
wire aes_lrclk;

ultranet_tx_clocks clocks(
    .mclk(i2s_in_sclk),         // 24.576 Mhz

	.i2s_bclk(i2s_in_bclk),     // 
	.i2s_lrclk(i2s_in_lrclk),   // 48 KHz

	.aes_bclk(aes_bclk),        // 12.288 Mhz
    .aes_lrclk(aes_lrclk)       // 192 KHz
);

//assign debug_4 = aes_lrclk;

wire [23:0] audio_sample_1;
wire [23:0] audio_sample_2;
wire [23:0] audio_sample_3;
wire [23:0] audio_sample_4;
wire [23:0] audio_sample_5;
wire [23:0] audio_sample_6;
wire [23:0] audio_sample_7;
wire [23:0] audio_sample_8;

wire i2s_new_data;

i2s_quad_deserializer deserializer(
	.clk(clk),
	.bsync(!reset_n),

	.bclk(i2s_in_bclk),
	.lrclk(i2s_in_lrclk),

	.sdata1(i2s_in_data_1),
	.sdata2(i2s_in_data_2),
	.sdata3(i2s_in_data_3),
	.sdata4(i2s_in_data_4),

	.sample_out_ch_1_l(audio_sample_1),
	.sample_out_ch_1_r(audio_sample_2),
	.sample_out_ch_2_l(audio_sample_3),
	.sample_out_ch_2_r(audio_sample_4),
	.sample_out_ch_3_l(audio_sample_5),
	.sample_out_ch_3_r(audio_sample_6),
	.sample_out_ch_4_l(audio_sample_7),
	.sample_out_ch_4_r(audio_sample_8),

	.new_data(i2s_new_data)
);

assign debug_3 = i2s_new_data;

wire [23:0] i2s_sample;


ultranet_serializer serializer(
	.clk(clk),

	.new_data(i2s_new_data),
    
    .aes_lrck(aes_lrclk),

	.ch1_in(audio_sample_1),
	.ch2_in(audio_sample_2),
	.ch3_in(audio_sample_3),
	.ch4_in(audio_sample_4),
	.ch5_in(audio_sample_5),
	.ch6_in(audio_sample_6),
	.ch7_in(audio_sample_7),
	.ch8_in(audio_sample_8),

    .ch_out(i2s_sample)
);


aes3tx transmitter(
    .bit_clock(aes_bclk),

    .sample(i2s_sample),

    .user_status(user_status),
    .channel_status(channel_status),
    .valid(valid),
        
    .bsync(bsync),

    .biphase_out(aes3_tx)
);



endmodule