-- create LRCLK from BCLK for I2S

LIBRARY IEEE;    
USE IEEE.STD_LOGIC_1164.ALL;    

entity ultranet_tx_clocks is
    port (
        mclk	    : in std_logic;

        i2s_bclk	: inout std_logic;
        i2s_lrclk	: inout std_logic;

        aes_bclk	: inout std_logic;
        aes_lrclk   : inout std_logic
    );
end entity;

architecture Behavioral of ultranet_tx_clocks is
    signal count_i2s_bclk : integer := 0;
    signal count_i2s_lrclk : integer := 0;
    signal count_aes_lrclk : integer := 0;
begin

    i2s_bit_clock: process(mclk)  begin
        if(rising_edge(mclk)) then
            count_i2s_bclk <= count_i2s_bclk + 1;
            if(count_i2s_bclk = 3) then
                i2s_bclk <= not i2s_bclk;
                count_i2s_bclk <=0;
            end if;
        end if;
    end process;

    i2s_lr_cloc: process(mclk) begin
        if(rising_edge(mclk)) then
            count_i2s_lrclk <= count_i2s_lrclk + 1;
            if(count_i2s_lrclk = 255) then
                i2s_lrclk <= not i2s_lrclk;
                count_i2s_lrclk <=0;
            end if;
        end if;
    end process;

    --aes_bclkaes_bclkaes_bclk: process(mclk) begin
    --    if(rising_edge(mclk)) then
    --        aes_bclk <= not aes_bclk;
    --    end if;
    --end process;
    aes_bclk <= mclk;

    aes_lr_clock: process(mclk) begin
        if(rising_edge(mclk)) then
            count_aes_lrclk <= count_aes_lrclk + 1;
            if(count_aes_lrclk = 63) then
                aes_lrclk <= not aes_lrclk;
                count_aes_lrclk <=0;
            end if;
        end if;
    end process;

end;