-------------------------------------------------------------------------------
-- Demuxer to split the incomming sound samples into 8 different channels
-- Based on 
--    - https://github.com/xn--nding-jua/UltranetReceiver
------------------------------------------------------------------------------- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all; -- lib for unsigned and signed

entity ultranet_rx_demux is
	port (
        -- Master clock
		clk				: in std_logic;

        -- Audio sample and destination channel
		sample_in		: in std_logic_vector(23 downto 0);
		channel			: in unsigned(2 downto 0);

        -- Data write signal
		new_data		: in std_logic;
		
        -- Output samples for each channel
		ch1_out 		: out std_logic_vector(23 downto 0);
		ch2_out 		: out std_logic_vector(23 downto 0);
		ch3_out 		: out std_logic_vector(23 downto 0);
		ch4_out 		: out std_logic_vector(23 downto 0);
		ch5_out 		: out std_logic_vector(23 downto 0);
		ch6_out 		: out std_logic_vector(23 downto 0);
		ch7_out 		: out std_logic_vector(23 downto 0);
		ch8_out 		: out std_logic_vector(23 downto 0)
	);
end entity;

architecture rtl of ultranet_rx_demux is
    -- New data detector & signal
	signal znew_data, zznew_data, zzznew_data	: std_logic;
    signal new_data_pos_edge		: std_logic;
begin

	detect_edge : process(clk) begin
		if rising_edge(clk) then
			znew_data <= new_data;
			zznew_data <= znew_data;
			zzznew_data <= zznew_data;
			if zznew_data = '1' and zzznew_data = '0' then
				new_data_pos_edge <= '1';
			else
				new_data_pos_edge <= '0';
			end if;
		end if;
	end process;

	process(clk) begin
		if (rising_edge(clk)) then
			-- Store individual channels to output-vectors on the rising edge of new data
			if new_data_pos_edge = '1' then
				if channel = 0 then
					ch1_out <= sample_in;
				elsif channel = 1 then
					ch2_out <= sample_in;
				elsif channel = 2 then
					ch3_out <= sample_in;
				elsif channel = 3 then
					ch4_out <= sample_in;
				elsif channel = 4 then
					ch5_out <= sample_in;
				elsif channel = 5 then
					ch6_out <= sample_in;
				elsif channel = 6 then
					ch7_out <= sample_in;
				elsif channel = 7 then
					ch8_out <= sample_in;
				end if;
			end if;
		end if;
	end process;
end rtl;