<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>beta</Version>
    <Device id="GW1NR-9C" package="QFN88P" speed="6" partNumber="GW1NR-LV9QN88PC6/I5"/>
    <FileList>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v" type="verilog"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v" type="verilog"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v" type="verilog"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v" type="verilog"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd" type="vhdl"/>
        <File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd" type="vhdl"/>
    </FileList>
    <OptionList>
        <Option type="disable_insert_pad" value="0"/>
        <Option type="global_freq" value="50.000"/>
        <Option type="looplimit" value="2000"/>
        <Option type="output_file" value="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg"/>
        <Option type="print_all_synthesis_warning" value="0"/>
        <Option type="ram_rw_check" value="0"/>
        <Option type="top_module" value="top"/>
        <Option type="vcc" value="1.2"/>
        <Option type="vccx" value="3.3"/>
        <Option type="verilog_language" value="verilog-2001"/>
        <Option type="vhdl_language" value="vhdl-1993"/>
    </OptionList>
</Project>
