Reading netlist file: "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg"
Parsing netlist file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg" completed
Processing netlist completed
Reading constraint file: "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
WARN  (TA1132) :  'main_rx_1_inst/aes3_bclk' was determined to be a clock but was not created.
WARN  (TA1117) : Can't calculate clocks' relationship between: "main_rx_1_inst/aes3_bclk" and "pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk"
WARN  (TA1117) : Can't calculate clocks' relationship between: "pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk" and "main_rx_1_inst/aes3_bclk"
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.power.html" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.pin.html" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.html" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.txt" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.tr.html" completed
Sat Oct  4 00:11:09 2025

