# Timing Analysis Report

# Timing Messages

Report Title | Timing Analysis Report
Design File | C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
Physical Constraints File | C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst
Timing Constraint File | C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\test_fpga_project.sdc
Tool Version | V1.9.10.03 Education (64-bit)
Part Number | GW1NR-LV9QN88PC6/I5
Device | GW1NR-9
Device Version | C
Created Time | Sat Oct 4 00:11:09 2025
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C C6/I5
Hold Delay Model | Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed | 9704
Numbers of Endpoints Analyzed | 4472
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 663
Numbers of Hold Violated Endpoints | 1

## Clock Summary:

NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
1 | i2s_in_sclk | Base | 40.690 | 24.576 | 0.000 | 20.345 |  |  | i2s_in_sclk_ibuf/I
2 | main_rx_1_inst/aes3_bclk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | main_rx_1_inst/receiver/sclk_s0/Q
3 | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Generated | 4.069 | 245.760 | 0.000 | 2.035 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUT
4 | pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Generated | 4.069 | 245.760 | 0.000 | 2.035 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTP
5 | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Generated | 8.138 | 122.880 | 0.000 | 4.069 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTD
6 | pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 12.207 | 81.920 | 0.000 | 6.104 | i2s_in_sclk_ibuf/I | i2s_in_sclk | pll_main_clock/rpll_inst/CLKOUTD3

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | i2s_in_sclk | 24.576(MHz) | 74.729(MHz) | 5 | TOP
2 | main_rx_1_inst/aes3_bclk | 50.000(MHz) | 148.663(MHz) | 4 | TOP
3 | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | 245.760(MHz) | 169.633(MHz) | 3 | TOP
4 | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | 122.880(MHz) | 102.090(MHz) | 5 | TOP

#### No timing paths to get frequency of pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
i2s_in_sclk | Setup | 0.000 | 0
i2s_in_sclk | Hold | 0.000 | 0
main_rx_1_inst/aes3_bclk | Setup | 0.000 | 0
main_rx_1_inst/aes3_bclk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Setup | -514.939 | 450
pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Setup | -5.361 | 6
pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
pll_main_clock/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -1.826 | main_tx_inst/serializer/channel_cnt_0_s3/Q | main_tx_inst/serializer/ch_out_6_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.495
2 | -1.817 | main_tx_inst2/serializer/channel_cnt_2_s1/Q | main_tx_inst2/serializer/ch_out_4_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.486
3 | -1.807 | main_tx_inst2/serializer/channel_cnt_2_s1/Q | main_tx_inst2/serializer/ch_out_19_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.476
4 | -1.803 | main_tx_inst2/serializer/channel_cnt_2_s1/Q | main_tx_inst2/serializer/ch_out_2_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.472
5 | -1.800 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.825
6 | -1.799 | main_tx_inst2/serializer/channel_cnt_2_s1/Q | main_tx_inst2/serializer/ch_out_12_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.468
7 | -1.796 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.821
8 | -1.792 | main_tx_inst/serializer/channel_cnt_0_s3/Q | main_tx_inst/serializer/ch_out_3_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.461
9 | -1.764 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_4_l_2_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.790
10 | -1.764 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.790
11 | -1.761 | main_tx_inst/serializer/channel_cnt_0_s3/Q | main_tx_inst/serializer/ch_out_11_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.430
12 | -1.752 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.778
13 | -1.748 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.774
14 | -1.745 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.770
15 | -1.745 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.770
16 | -1.745 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.770
17 | -1.742 | main_tx_inst/serializer/channel_cnt_0_s3/Q | main_tx_inst/serializer/ch_out_22_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.412
18 | -1.719 | main_tx_inst/serializer/channel_cnt_0_s3/Q | main_tx_inst/serializer/ch_out_8_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.388
19 | -1.713 | main_tx_inst2/serializer/channel_cnt_0_s3/Q | main_tx_inst2/serializer/ch_out_14_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.382
20 | -1.713 | main_tx_inst2/serializer/channel_cnt_0_s3/Q | main_tx_inst2/serializer/ch_out_15_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.382
21 | -1.707 | main_tx_inst2/serializer/channel_cnt_1_s3/Q | main_tx_inst2/serializer/ch_out_7_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.376
22 | -1.707 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.732
23 | -1.707 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.732
24 | -1.702 | main_tx_inst2/serializer/channel_cnt_0_s3/Q | main_tx_inst2/serializer/ch_out_18_s0/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.371
25 | -1.700 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst2/deserializer/sample_out_ch_4_l_21_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 4.069 | 0.000 | 5.725

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -0.141 | main_tx_inst2/clocks/i2s_bclk_s2/Q | main_tx_inst2/deserializer/zbclk_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 0.984
2 | 0.379 | main_tx_inst/clocks/i2s_lrclk_s2/Q | main_tx_inst/deserializer/zlrclk_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.505
3 | 0.389 | main_tx_inst2/clocks/i2s_lrclk_s2/Q | main_tx_inst2/deserializer/zlrclk_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.514
4 | 0.407 | main_tx_inst/clocks/i2s_bclk_s2/Q | main_tx_inst/deserializer/zbclk_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.532
5 | 0.425 | main_tx_inst/clocks/aes_lrclk_s2/Q | main_tx_inst/serializer/zaes_lrck_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.550
6 | 0.506 | main_tx_inst/clocks/i2s_lrclk_s2/Q | main_tx_inst/deserializer/new_data_s0/D | i2s_in_sclk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -1.095 | 1.631
7 | 0.558 | main_rx_1_inst/demuxer/zznew_data_s0/Q | main_rx_1_inst/demuxer/new_data_pos_edge_s0/RESET | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.571
8 | 0.558 | main_rx_1_inst/clocks/zzbsync_s0/Q | main_rx_1_inst/clocks/bsync_pos_edge_s0/RESET | main_rx_1_inst/aes3_bclk:[R] | main_rx_1_inst/aes3_bclk:[R] | 0.000 | 0.000 | 0.571
9 | 0.561 | main_rx_1_inst/receiver/aes3_clk_s0/Q | main_rx_1_inst/receiver/decoder_shift_7_s0/CE | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.573
10 | 0.565 | main_rx_1_inst/clocks/zzaes_lrclk_s0/Q | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/RESET | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | 0.000 | 0.000 | 0.577
11 | 0.567 | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | main_tx_inst/deserializer/new_data_s0/RESET | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.579
12 | 0.590 | main_tx_inst/deserializer/zzbsync_s0/Q | main_tx_inst/deserializer/bsync_pos_edge_s0/RESET | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.602
13 | 0.595 | main_tx_inst2/serializer/aes_lrck_edge_s0/Q | main_tx_inst2/serializer/ch_out_1_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.608
14 | 0.599 | main_tx_inst2/serializer/aes_lrck_edge_s0/Q | main_tx_inst2/serializer/ch_out_4_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.611
15 | 0.603 | main_tx_inst2/serializer/aes_lrck_edge_s0/Q | main_tx_inst2/serializer/ch_out_7_s0/CE | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.615
16 | 0.708 | main_tx_inst/deserializer/bit_cnt_4_s4/Q | main_tx_inst/deserializer/bit_cnt_4_s4/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
17 | 0.708 | main_tx_inst/deserializer/lrck_neg_edge_s4/Q | main_tx_inst/deserializer/lrck_neg_edge_s4/D | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.708
18 | 0.708 | main_tx_inst2/transmitter/data_biphase_s1/Q | main_tx_inst2/transmitter/data_biphase_s1/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
19 | 0.708 | main_tx_inst2/clocks/aes_lrclk_s2/Q | main_tx_inst2/clocks/aes_lrclk_s2/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
20 | 0.708 | main_tx_inst2/clocks/i2s_bclk_s2/Q | main_tx_inst2/clocks/i2s_bclk_s2/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
21 | 0.708 | main_tx_inst2/clocks/count_aes_lrclk_0_s0/Q | main_tx_inst2/clocks/count_aes_lrclk_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
22 | 0.708 | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/Q | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
23 | 0.708 | main_tx_inst2/clocks/count_i2s_bclk_0_s0/Q | main_tx_inst2/clocks/count_i2s_bclk_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
24 | 0.708 | main_tx_inst/clocks/aes_lrclk_s2/Q | main_tx_inst/clocks/aes_lrclk_s2/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708
25 | 0.708 | main_tx_inst/clocks/count_aes_lrclk_0_s0/Q | main_tx_inst/clocks/count_aes_lrclk_0_s0/D | i2s_in_sclk:[R] | i2s_in_sclk:[R] | 0.000 | 0.000 | 0.708

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/zzbsync_s0
2 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/zzzbsync_s0
3 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_1_r_9_s0
4 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_r_21_s0
5 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_3_r_5_s0
6 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_4_r_19_s0
7 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_4_r_15_s0
8 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_4_r_13_s0
9 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst/deserializer/sample_out_ch_4_r_12_s0
10 | 0.707 | 1.957 | 1.250 | Low Pulse Width | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | main_tx_inst2/deserializer/sample_out_ch_1_r_15_s0

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -1.826
Data Arrival Time | 8.226
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_0_s3
To | main_tx_inst/serializer/ch_out_6_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/Q
4.498 | 1.308 | tNET | FF | 1 | R12C22[0][B] | main_tx_inst/serializer/n381_s12/I0
5.124 | 0.626 | tINS | FF | 22 | R12C22[0][B] | main_tx_inst/serializer/n381_s12/F
7.265 | 2.142 | tNET | FF | 1 | R9C28[3][A] | main_tx_inst/serializer/n398_s13/I2
7.890 | 0.625 | tINS | FR | 1 | R9C28[3][A] | main_tx_inst/serializer/n398_s13/F
7.890 | 0.000 | tNET | RR | 1 | R9C28[3][A] | main_tx_inst/serializer/n398_s9/I0
8.040 | 0.150 | tINS | RR | 1 | R9C28[3][A] | main_tx_inst/serializer/n398_s9/O
8.040 | 0.000 | tNET | RR | 1 | R9C28[2][B] | main_tx_inst/serializer/n398_s5/I0
8.217 | 0.177 | tINS | RR | 1 | R9C28[2][B] | main_tx_inst/serializer/n398_s5/O
8.226 | 0.009 | tNET | RR | 1 | R9C28[2][B] | main_tx_inst/serializer/ch_out_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C28[2][B] | main_tx_inst/serializer/ch_out_6_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C28[2][B] | main_tx_inst/serializer/ch_out_6_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.578, 28.717%; route: 3.459, 62.943%; tC2Q: 0.458, 8.341%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path2

Path Summary:

Slack | -1.817
Data Arrival Time | 8.218
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_2_s1
To | main_tx_inst2/serializer/ch_out_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 30 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/Q
4.380 | 1.191 | tNET | FF | 1 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/I1
5.412 | 1.032 | tINS | FF | 22 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/F
7.257 | 1.845 | tNET | FF | 1 | R6C12[3][B] | main_tx_inst2/serializer/n400_s14/I2
7.882 | 0.625 | tINS | FR | 1 | R6C12[3][B] | main_tx_inst2/serializer/n400_s14/F
7.882 | 0.000 | tNET | RR | 1 | R6C12[3][A] | main_tx_inst2/serializer/n400_s9/I1
8.032 | 0.150 | tINS | RR | 1 | R6C12[3][A] | main_tx_inst2/serializer/n400_s9/O
8.032 | 0.000 | tNET | RR | 1 | R6C12[2][B] | main_tx_inst2/serializer/n400_s5/I0
8.209 | 0.177 | tINS | RR | 1 | R6C12[2][B] | main_tx_inst2/serializer/n400_s5/O
8.218 | 0.009 | tNET | RR | 1 | R6C12[2][B] | main_tx_inst2/serializer/ch_out_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R6C12[2][B] | main_tx_inst2/serializer/ch_out_4_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R6C12[2][B] | main_tx_inst2/serializer/ch_out_4_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.984, 36.162%; route: 3.044, 55.484%; tC2Q: 0.458, 8.354%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path3

Path Summary:

Slack | -1.807
Data Arrival Time | 8.207
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_2_s1
To | main_tx_inst2/serializer/ch_out_19_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 30 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/Q
4.380 | 1.191 | tNET | FF | 1 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/I1
5.412 | 1.032 | tINS | FF | 22 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/F
7.246 | 1.834 | tNET | FF | 1 | R12C11[3][B] | main_tx_inst2/serializer/n385_s14/I2
7.871 | 0.625 | tINS | FR | 1 | R12C11[3][B] | main_tx_inst2/serializer/n385_s14/F
7.871 | 0.000 | tNET | RR | 1 | R12C11[3][A] | main_tx_inst2/serializer/n385_s9/I1
8.021 | 0.150 | tINS | RR | 1 | R12C11[3][A] | main_tx_inst2/serializer/n385_s9/O
8.021 | 0.000 | tNET | RR | 1 | R12C11[2][B] | main_tx_inst2/serializer/n385_s5/I0
8.198 | 0.177 | tINS | RR | 1 | R12C11[2][B] | main_tx_inst2/serializer/n385_s5/O
8.207 | 0.009 | tNET | RR | 1 | R12C11[2][B] | main_tx_inst2/serializer/ch_out_19_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C11[2][B] | main_tx_inst2/serializer/ch_out_19_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R12C11[2][B] | main_tx_inst2/serializer/ch_out_19_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.984, 36.233%; route: 3.033, 55.397%; tC2Q: 0.458, 8.370%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path4

Path Summary:

Slack | -1.803
Data Arrival Time | 8.203
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_2_s1
To | main_tx_inst2/serializer/ch_out_2_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 30 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/Q
4.380 | 1.191 | tNET | FF | 1 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/I1
5.412 | 1.032 | tINS | FF | 22 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/F
6.777 | 1.365 | tNET | FF | 1 | R6C7[3][B] | main_tx_inst2/serializer/n402_s14/I2
7.876 | 1.099 | tINS | FF | 1 | R6C7[3][B] | main_tx_inst2/serializer/n402_s14/F
7.876 | 0.000 | tNET | FF | 1 | R6C7[3][A] | main_tx_inst2/serializer/n402_s9/I1
8.025 | 0.149 | tINS | FF | 1 | R6C7[3][A] | main_tx_inst2/serializer/n402_s9/O
8.025 | 0.000 | tNET | FF | 1 | R6C7[2][B] | main_tx_inst2/serializer/n402_s5/I0
8.188 | 0.163 | tINS | FF | 1 | R6C7[2][B] | main_tx_inst2/serializer/n402_s5/O
8.203 | 0.015 | tNET | FF | 1 | R6C7[2][B] | main_tx_inst2/serializer/ch_out_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R6C7[2][B] | main_tx_inst2/serializer/ch_out_2_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R6C7[2][B] | main_tx_inst2/serializer/ch_out_2_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.443, 44.644%; route: 2.571, 46.980%; tC2Q: 0.458, 8.376%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path5

Path Summary:

Slack | -1.800
Data Arrival Time | 8.557
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.557 | 1.645 | tNET | RR | 1 | R9C5[2][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C5[2][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R9C5[2][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.729%; route: 4.742, 81.403%; tC2Q: 0.458, 7.868%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path6

Path Summary:

Slack | -1.799
Data Arrival Time | 8.199
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_2_s1
To | main_tx_inst2/serializer/ch_out_12_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/CLK
3.190 | 0.458 | tC2Q | RF | 30 | R8C10[2][A] | main_tx_inst2/serializer/channel_cnt_2_s1/Q
4.380 | 1.191 | tNET | FF | 1 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/I1
5.412 | 1.032 | tINS | FF | 22 | R9C8[3][B] | main_tx_inst2/serializer/n333_s6/F
6.773 | 1.361 | tNET | FF | 1 | R12C7[3][B] | main_tx_inst2/serializer/n392_s14/I2
7.872 | 1.099 | tINS | FF | 1 | R12C7[3][B] | main_tx_inst2/serializer/n392_s14/F
7.872 | 0.000 | tNET | FF | 1 | R12C7[3][A] | main_tx_inst2/serializer/n392_s9/I1
8.021 | 0.149 | tINS | FF | 1 | R12C7[3][A] | main_tx_inst2/serializer/n392_s9/O
8.021 | 0.000 | tNET | FF | 1 | R12C7[2][B] | main_tx_inst2/serializer/n392_s5/I0
8.184 | 0.163 | tINS | FF | 1 | R12C7[2][B] | main_tx_inst2/serializer/n392_s5/O
8.199 | 0.015 | tNET | FF | 1 | R12C7[2][B] | main_tx_inst2/serializer/ch_out_12_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C7[2][B] | main_tx_inst2/serializer/ch_out_12_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R12C7[2][B] | main_tx_inst2/serializer/ch_out_12_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.443, 44.681%; route: 2.566, 46.936%; tC2Q: 0.458, 8.383%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path7

Path Summary:

Slack | -1.796
Data Arrival Time | 8.553
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.553 | 1.641 | tNET | RR | 1 | R8C14[2][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R8C14[2][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R8C14[2][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.736%; route: 4.738, 81.391%; tC2Q: 0.458, 7.873%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path8

Path Summary:

Slack | -1.792
Data Arrival Time | 8.192
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_0_s3
To | main_tx_inst/serializer/ch_out_3_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/Q
4.018 | 0.828 | tNET | FF | 1 | R11C22[1][A] | main_tx_inst/serializer/n237_s2/I0
5.050 | 1.032 | tINS | FF | 22 | R11C22[1][A] | main_tx_inst/serializer/n237_s2/F
7.043 | 1.993 | tNET | FF | 1 | R8C28[2][B] | main_tx_inst/serializer/n401_s12/I2
7.865 | 0.822 | tINS | FF | 1 | R8C28[2][B] | main_tx_inst/serializer/n401_s12/F
7.865 | 0.000 | tNET | FF | 1 | R8C28[2][A] | main_tx_inst/serializer/n401_s10/I1
8.014 | 0.149 | tINS | FF | 1 | R8C28[2][A] | main_tx_inst/serializer/n401_s10/O
8.014 | 0.000 | tNET | FF | 1 | R8C28[2][B] | main_tx_inst/serializer/n401_s5/I1
8.177 | 0.163 | tINS | FF | 1 | R8C28[2][B] | main_tx_inst/serializer/n401_s5/O
8.192 | 0.015 | tNET | FF | 1 | R8C28[2][B] | main_tx_inst/serializer/ch_out_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R8C28[2][B] | main_tx_inst/serializer/ch_out_3_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R8C28[2][B] | main_tx_inst/serializer/ch_out_3_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.166, 39.666%; route: 2.836, 51.941%; tC2Q: 0.458, 8.393%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path9

Path Summary:

Slack | -1.764
Data Arrival Time | 8.521
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_4_l_2_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.521 | 1.609 | tNET | RR | 1 | R7C6[0][B] | main_tx_inst2/deserializer/sample_out_ch_4_l_2_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R7C6[0][B] | main_tx_inst2/deserializer/sample_out_ch_4_l_2_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R7C6[0][B] | main_tx_inst2/deserializer/sample_out_ch_4_l_2_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.794%; route: 4.707, 81.290%; tC2Q: 0.458, 7.916%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path10

Path Summary:

Slack | -1.764
Data Arrival Time | 8.521
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.521 | 1.609 | tNET | RR | 1 | R7C6[0][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R7C6[0][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R7C6[0][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.794%; route: 4.707, 81.290%; tC2Q: 0.458, 7.916%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path11

Path Summary:

Slack | -1.761
Data Arrival Time | 8.162
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_0_s3
To | main_tx_inst/serializer/ch_out_11_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/Q
4.018 | 0.828 | tNET | FF | 1 | R11C22[1][A] | main_tx_inst/serializer/n237_s2/I0
5.050 | 1.032 | tINS | FF | 22 | R11C22[1][A] | main_tx_inst/serializer/n237_s2/F
6.736 | 1.686 | tNET | FF | 1 | R13C28[2][B] | main_tx_inst/serializer/n393_s12/I2
7.835 | 1.099 | tINS | FF | 1 | R13C28[2][B] | main_tx_inst/serializer/n393_s12/F
7.835 | 0.000 | tNET | FF | 1 | R13C28[2][A] | main_tx_inst/serializer/n393_s10/I1
7.984 | 0.149 | tINS | FF | 1 | R13C28[2][A] | main_tx_inst/serializer/n393_s10/O
7.984 | 0.000 | tNET | FF | 1 | R13C28[2][B] | main_tx_inst/serializer/n393_s5/I1
8.147 | 0.163 | tINS | FF | 1 | R13C28[2][B] | main_tx_inst/serializer/n393_s5/O
8.162 | 0.015 | tNET | FF | 1 | R13C28[2][B] | main_tx_inst/serializer/ch_out_11_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R13C28[2][B] | main_tx_inst/serializer/ch_out_11_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R13C28[2][B] | main_tx_inst/serializer/ch_out_11_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.443, 44.988%; route: 2.529, 46.572%; tC2Q: 0.458, 8.440%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path12

Path Summary:

Slack | -1.752
Data Arrival Time | 8.509
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.509 | 1.597 | tNET | RR | 1 | R12C5[0][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R12C5[0][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R12C5[0][A] | main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.818%; route: 4.694, 81.249%; tC2Q: 0.458, 7.933%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path13

Path Summary:

Slack | -1.748
Data Arrival Time | 8.505
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.505 | 1.593 | tNET | RR | 1 | R7C14[1][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R7C14[1][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R7C14[1][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.825%; route: 4.690, 81.236%; tC2Q: 0.458, 7.938%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path14

Path Summary:

Slack | -1.745
Data Arrival Time | 8.502
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.502 | 1.590 | tNET | RR | 1 | R11C13[0][B] | main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C13[0][B] | main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R11C13[0][B] | main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.831%; route: 4.687, 81.226%; tC2Q: 0.458, 7.943%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path15

Path Summary:

Slack | -1.745
Data Arrival Time | 8.502
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.502 | 1.590 | tNET | RR | 1 | R11C13[0][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C13[0][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R11C13[0][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.831%; route: 4.687, 81.226%; tC2Q: 0.458, 7.943%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path16

Path Summary:

Slack | -1.745
Data Arrival Time | 8.502
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.502 | 1.590 | tNET | RR | 1 | R11C13[1][B] | main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C13[1][B] | main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R11C13[1][B] | main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.831%; route: 4.687, 81.226%; tC2Q: 0.458, 7.943%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path17

Path Summary:

Slack | -1.742
Data Arrival Time | 8.143
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_0_s3
To | main_tx_inst/serializer/ch_out_22_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/Q
4.498 | 1.308 | tNET | FF | 1 | R12C22[0][B] | main_tx_inst/serializer/n381_s12/I0
5.124 | 0.626 | tINS | FF | 22 | R12C22[0][B] | main_tx_inst/serializer/n381_s12/F
6.781 | 1.657 | tNET | FF | 1 | R11C28[3][A] | main_tx_inst/serializer/n382_s13/I2
7.807 | 1.026 | tINS | FR | 1 | R11C28[3][A] | main_tx_inst/serializer/n382_s13/F
7.807 | 0.000 | tNET | RR | 1 | R11C28[3][A] | main_tx_inst/serializer/n382_s9/I0
7.957 | 0.150 | tINS | RR | 1 | R11C28[3][A] | main_tx_inst/serializer/n382_s9/O
7.957 | 0.000 | tNET | RR | 1 | R11C28[2][B] | main_tx_inst/serializer/n382_s5/I0
8.134 | 0.177 | tINS | RR | 1 | R11C28[2][B] | main_tx_inst/serializer/n382_s5/O
8.143 | 0.009 | tNET | RR | 1 | R11C28[2][B] | main_tx_inst/serializer/ch_out_22_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C28[2][B] | main_tx_inst/serializer/ch_out_22_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C28[2][B] | main_tx_inst/serializer/ch_out_22_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.979, 36.570%; route: 2.974, 54.960%; tC2Q: 0.458, 8.470%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path18

Path Summary:

Slack | -1.719
Data Arrival Time | 8.119
Data Required Time | 6.400
From | main_tx_inst/serializer/channel_cnt_0_s3
To | main_tx_inst/serializer/ch_out_8_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R9C21[0][A] | main_tx_inst/serializer/channel_cnt_0_s3/Q
4.498 | 1.308 | tNET | FF | 1 | R12C22[0][B] | main_tx_inst/serializer/n381_s12/I0
5.124 | 0.626 | tINS | FF | 22 | R12C22[0][B] | main_tx_inst/serializer/n381_s12/F
6.970 | 1.846 | tNET | FF | 1 | R9C25[3][A] | main_tx_inst/serializer/n396_s13/I2
7.792 | 0.822 | tINS | FF | 1 | R9C25[3][A] | main_tx_inst/serializer/n396_s13/F
7.792 | 0.000 | tNET | FF | 1 | R9C25[3][A] | main_tx_inst/serializer/n396_s9/I0
7.941 | 0.149 | tINS | FF | 1 | R9C25[3][A] | main_tx_inst/serializer/n396_s9/O
7.941 | 0.000 | tNET | FF | 1 | R9C25[2][B] | main_tx_inst/serializer/n396_s5/I0
8.104 | 0.163 | tINS | FF | 1 | R9C25[2][B] | main_tx_inst/serializer/n396_s5/O
8.119 | 0.015 | tNET | FF | 1 | R9C25[2][B] | main_tx_inst/serializer/ch_out_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C25[2][B] | main_tx_inst/serializer/ch_out_8_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C25[2][B] | main_tx_inst/serializer/ch_out_8_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 1.760, 32.668%; route: 3.169, 58.825%; tC2Q: 0.458, 8.507%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path19

Path Summary:

Slack | -1.713
Data Arrival Time | 8.113
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_0_s3
To | main_tx_inst2/serializer/ch_out_14_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C11[1][A] | main_tx_inst2/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R8C11[1][A] | main_tx_inst2/serializer/channel_cnt_0_s3/Q
4.510 | 1.320 | tNET | FF | 1 | R8C8[3][A] | main_tx_inst2/serializer/n237_s2/I0
5.332 | 0.822 | tINS | FF | 22 | R8C8[3][A] | main_tx_inst2/serializer/n237_s2/F
6.687 | 1.355 | tNET | FF | 1 | R11C9[2][B] | main_tx_inst2/serializer/n390_s12/I2
7.786 | 1.099 | tINS | FF | 1 | R11C9[2][B] | main_tx_inst2/serializer/n390_s12/F
7.786 | 0.000 | tNET | FF | 1 | R11C9[2][A] | main_tx_inst2/serializer/n390_s10/I1
7.935 | 0.149 | tINS | FF | 1 | R11C9[2][A] | main_tx_inst2/serializer/n390_s10/O
7.935 | 0.000 | tNET | FF | 1 | R11C9[2][B] | main_tx_inst2/serializer/n390_s5/I1
8.098 | 0.163 | tINS | FF | 1 | R11C9[2][B] | main_tx_inst2/serializer/n390_s5/O
8.113 | 0.015 | tNET | FF | 1 | R11C9[2][B] | main_tx_inst2/serializer/ch_out_14_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R11C9[2][B] | main_tx_inst2/serializer/ch_out_14_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R11C9[2][B] | main_tx_inst2/serializer/ch_out_14_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 41.489%; route: 2.691, 49.995%; tC2Q: 0.458, 8.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path20

Path Summary:

Slack | -1.713
Data Arrival Time | 8.113
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_0_s3
To | main_tx_inst2/serializer/ch_out_15_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C11[1][A] | main_tx_inst2/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R8C11[1][A] | main_tx_inst2/serializer/channel_cnt_0_s3/Q
4.510 | 1.320 | tNET | FF | 1 | R8C8[3][A] | main_tx_inst2/serializer/n237_s2/I0
5.332 | 0.822 | tINS | FF | 22 | R8C8[3][A] | main_tx_inst2/serializer/n237_s2/F
6.687 | 1.355 | tNET | FF | 1 | R9C6[2][B] | main_tx_inst2/serializer/n389_s12/I2
7.786 | 1.099 | tINS | FF | 1 | R9C6[2][B] | main_tx_inst2/serializer/n389_s12/F
7.786 | 0.000 | tNET | FF | 1 | R9C6[2][A] | main_tx_inst2/serializer/n389_s10/I1
7.935 | 0.149 | tINS | FF | 1 | R9C6[2][A] | main_tx_inst2/serializer/n389_s10/O
7.935 | 0.000 | tNET | FF | 1 | R9C6[2][B] | main_tx_inst2/serializer/n389_s5/I1
8.098 | 0.163 | tINS | FF | 1 | R9C6[2][B] | main_tx_inst2/serializer/n389_s5/O
8.113 | 0.015 | tNET | FF | 1 | R9C6[2][B] | main_tx_inst2/serializer/ch_out_15_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C6[2][B] | main_tx_inst2/serializer/ch_out_15_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C6[2][B] | main_tx_inst2/serializer/ch_out_15_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 41.489%; route: 2.691, 49.995%; tC2Q: 0.458, 8.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path21

Path Summary:

Slack | -1.707
Data Arrival Time | 8.108
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_1_s3
To | main_tx_inst2/serializer/ch_out_7_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C10[0][A] | main_tx_inst2/serializer/channel_cnt_1_s3/CLK
3.190 | 0.458 | tC2Q | RF | 9 | R8C10[0][A] | main_tx_inst2/serializer/channel_cnt_1_s3/Q
4.009 | 0.819 | tNET | FF | 1 | R9C11[1][B] | main_tx_inst2/serializer/n285_s9/I1
5.108 | 1.099 | tINS | FF | 22 | R9C11[1][B] | main_tx_inst2/serializer/n285_s9/F
6.959 | 1.851 | tNET | FF | 1 | R6C8[2][A] | main_tx_inst2/serializer/n397_s11/I2
7.781 | 0.822 | tINS | FF | 1 | R6C8[2][A] | main_tx_inst2/serializer/n397_s11/F
7.781 | 0.000 | tNET | FF | 1 | R6C8[2][A] | main_tx_inst2/serializer/n397_s10/I0
7.930 | 0.149 | tINS | FF | 1 | R6C8[2][A] | main_tx_inst2/serializer/n397_s10/O
7.930 | 0.000 | tNET | FF | 1 | R6C8[2][B] | main_tx_inst2/serializer/n397_s5/I1
8.093 | 0.163 | tINS | FF | 1 | R6C8[2][B] | main_tx_inst2/serializer/n397_s5/O
8.108 | 0.015 | tNET | FF | 1 | R6C8[2][B] | main_tx_inst2/serializer/ch_out_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R6C8[2][B] | main_tx_inst2/serializer/ch_out_7_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R6C8[2][B] | main_tx_inst2/serializer/ch_out_7_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 41.533%; route: 2.685, 49.942%; tC2Q: 0.458, 8.525%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path22

Path Summary:

Slack | -1.707
Data Arrival Time | 8.464
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.464 | 1.552 | tNET | RR | 1 | R7C9[0][B] | main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R7C9[0][B] | main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R7C9[0][B] | main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.903%; route: 4.649, 81.102%; tC2Q: 0.458, 7.995%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path23

Path Summary:

Slack | -1.707
Data Arrival Time | 8.464
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.464 | 1.552 | tNET | RR | 1 | R7C9[0][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R7C9[0][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R7C9[0][A] | main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.903%; route: 4.649, 81.102%; tC2Q: 0.458, 7.995%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path24

Path Summary:

Slack | -1.702
Data Arrival Time | 8.102
Data Required Time | 6.400
From | main_tx_inst2/serializer/channel_cnt_0_s3
To | main_tx_inst2/serializer/ch_out_18_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R8C11[1][A] | main_tx_inst2/serializer/channel_cnt_0_s3/CLK
3.190 | 0.458 | tC2Q | RF | 7 | R8C11[1][A] | main_tx_inst2/serializer/channel_cnt_0_s3/Q
4.510 | 1.320 | tNET | FF | 1 | R8C8[3][A] | main_tx_inst2/serializer/n237_s2/I0
5.332 | 0.822 | tINS | FF | 22 | R8C8[3][A] | main_tx_inst2/serializer/n237_s2/F
6.676 | 1.344 | tNET | FF | 1 | R9C11[2][B] | main_tx_inst2/serializer/n386_s12/I2
7.775 | 1.099 | tINS | FF | 1 | R9C11[2][B] | main_tx_inst2/serializer/n386_s12/F
7.775 | 0.000 | tNET | FF | 1 | R9C11[2][A] | main_tx_inst2/serializer/n386_s10/I1
7.924 | 0.149 | tINS | FF | 1 | R9C11[2][A] | main_tx_inst2/serializer/n386_s10/O
7.924 | 0.000 | tNET | FF | 1 | R9C11[2][B] | main_tx_inst2/serializer/n386_s5/I1
8.087 | 0.163 | tINS | FF | 1 | R9C11[2][B] | main_tx_inst2/serializer/n386_s5/O
8.102 | 0.015 | tNET | FF | 1 | R9C11[2][B] | main_tx_inst2/serializer/ch_out_18_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C11[2][B] | main_tx_inst2/serializer/ch_out_18_s0/CLK
6.400 | -0.400 | tSu |  | 1 | R9C11[2][B] | main_tx_inst2/serializer/ch_out_18_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 2.233, 41.577%; route: 2.679, 49.889%; tC2Q: 0.458, 8.534%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Path25

Path Summary:

Slack | -1.700
Data Arrival Time | 8.457
Data Required Time | 6.757
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst2/deserializer/sample_out_ch_4_l_21_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.731 | 0.244 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.190 | 0.458 | tC2Q | RF | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
6.287 | 3.097 | tNET | FF | 1 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/I0
6.912 | 0.625 | tINS | FR | 88 | R15C10[1][A] | main_tx_inst2/deserializer/n1844_s1/F
8.457 | 1.545 | tNET | RR | 1 | R9C13[1][A] | main_tx_inst2/deserializer/sample_out_ch_4_l_21_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
4.069 | 4.069 |  |  |  |  | active clock edge time
4.069 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
6.800 | 0.244 | tNET | RR | 1 | R9C13[1][A] | main_tx_inst2/deserializer/sample_out_ch_4_l_21_s0/CLK
6.757 | -0.043 | tSu |  | 1 | R9C13[1][A] | main_tx_inst2/deserializer/sample_out_ch_4_l_21_s0

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 4.069
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay | cell: 0.625, 10.916%; route: 4.642, 81.079%; tC2Q: 0.458, 8.005%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -0.141
Data Arrival Time | 2.561
Data Required Time | 2.702
From | main_tx_inst2/clocks/i2s_bclk_s2
To | main_tx_inst2/deserializer/zbclk_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2/Q
2.561 | 0.651 | tNET | RR | 1 | R23C14[1][A] | main_tx_inst2/deserializer/zbclk_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R23C14[1][A] | main_tx_inst2/deserializer/zbclk_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst2/deserializer/zbclk_s0
2.702 | 0.000 | tHld |  | 1 | R23C14[1][A] | main_tx_inst2/deserializer/zbclk_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.651, 66.140%; tC2Q: 0.333, 33.860%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path2

Path Summary:

Slack | 0.379
Data Arrival Time | 3.081
Data Required Time | 2.702
From | main_tx_inst/clocks/i2s_lrclk_s2
To | main_tx_inst/deserializer/zlrclk_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R24C28[2][A] | main_tx_inst/clocks/i2s_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 6 | R24C28[2][A] | main_tx_inst/clocks/i2s_lrclk_s2/Q
3.081 | 1.172 | tNET | RR | 1 | R16C26[2][B] | main_tx_inst/deserializer/zlrclk_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R16C26[2][B] | main_tx_inst/deserializer/zlrclk_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst/deserializer/zlrclk_s0
2.702 | 0.000 | tHld |  | 1 | R16C26[2][B] | main_tx_inst/deserializer/zlrclk_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.172, 77.849%; tC2Q: 0.333, 22.151%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path3

Path Summary:

Slack | 0.389
Data Arrival Time | 3.091
Data Required Time | 2.702
From | main_tx_inst2/clocks/i2s_lrclk_s2
To | main_tx_inst2/deserializer/zlrclk_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R18C16[1][B] | main_tx_inst2/clocks/i2s_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 5 | R18C16[1][B] | main_tx_inst2/clocks/i2s_lrclk_s2/Q
3.091 | 1.181 | tNET | RR | 1 | R16C12[2][B] | main_tx_inst2/deserializer/zlrclk_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R16C12[2][B] | main_tx_inst2/deserializer/zlrclk_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst2/deserializer/zlrclk_s0
2.702 | 0.000 | tHld |  | 1 | R16C12[2][B] | main_tx_inst2/deserializer/zlrclk_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 77.988%; tC2Q: 0.333, 22.012%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path4

Path Summary:

Slack | 0.407
Data Arrival Time | 3.109
Data Required Time | 2.702
From | main_tx_inst/clocks/i2s_bclk_s2
To | main_tx_inst/deserializer/zbclk_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R24C22[0][A] | main_tx_inst/clocks/i2s_bclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R24C22[0][A] | main_tx_inst/clocks/i2s_bclk_s2/Q
3.109 | 1.199 | tNET | RR | 1 | R22C32[0][A] | main_tx_inst/deserializer/zbclk_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C32[0][A] | main_tx_inst/deserializer/zbclk_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst/deserializer/zbclk_s0
2.702 | 0.000 | tHld |  | 1 | R22C32[0][A] | main_tx_inst/deserializer/zbclk_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.199, 78.245%; tC2Q: 0.333, 21.755%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path5

Path Summary:

Slack | 0.425
Data Arrival Time | 3.127
Data Required Time | 2.702
From | main_tx_inst/clocks/aes_lrclk_s2
To | main_tx_inst/serializer/zaes_lrck_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/Q
3.127 | 1.217 | tNET | RR | 1 | R9C26[2][A] | main_tx_inst/serializer/zaes_lrck_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R9C26[2][A] | main_tx_inst/serializer/zaes_lrck_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst/serializer/zaes_lrck_s0
2.702 | 0.000 | tHld |  | 1 | R9C26[2][A] | main_tx_inst/serializer/zaes_lrck_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.217, 78.496%; tC2Q: 0.333, 21.504%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path6

Path Summary:

Slack | 0.506
Data Arrival Time | 3.208
Data Required Time | 2.702
From | main_tx_inst/clocks/i2s_lrclk_s2
To | main_tx_inst/deserializer/new_data_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R24C28[2][A] | main_tx_inst/clocks/i2s_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 6 | R24C28[2][A] | main_tx_inst/clocks/i2s_lrclk_s2/Q
2.484 | 0.574 | tNET | RR | 1 | R22C29[1][B] | main_tx_inst/deserializer/n74_s0/I0
3.208 | 0.724 | tINS | RR | 1 | R22C29[1][B] | main_tx_inst/deserializer/n74_s0/F
3.208 | 0.000 | tNET | RR | 1 | R22C29[1][B] | main_tx_inst/deserializer/new_data_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C29[1][B] | main_tx_inst/deserializer/new_data_s0/CLK
2.702 | 0.030 | tUnc |  |  |  | main_tx_inst/deserializer/new_data_s0
2.702 | 0.000 | tHld |  | 1 | R22C29[1][B] | main_tx_inst/deserializer/new_data_s0

Path Statistics:

Clock Skew | 1.095
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.724, 44.383%; route: 0.574, 35.183%; tC2Q: 0.333, 20.434%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path7

Path Summary:

Slack | 0.558
Data Arrival Time | 3.185
Data Required Time | 2.626
From | main_rx_1_inst/demuxer/zznew_data_s0
To | main_rx_1_inst/demuxer/new_data_pos_edge_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R17C33[1][A] | main_rx_1_inst/demuxer/zznew_data_s0/CLK
2.947 | 0.333 | tC2Q | RR | 2 | R17C33[1][A] | main_rx_1_inst/demuxer/zznew_data_s0/Q
3.185 | 0.238 | tNET | RR | 1 | R17C33[0][A] | main_rx_1_inst/demuxer/new_data_pos_edge_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R17C33[0][A] | main_rx_1_inst/demuxer/new_data_pos_edge_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R17C33[0][A] | main_rx_1_inst/demuxer/new_data_pos_edge_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path8

Path Summary:

Slack | 0.558
Data Arrival Time | 1.890
Data Required Time | 1.332
From | main_rx_1_inst/clocks/zzbsync_s0
To | main_rx_1_inst/clocks/bsync_pos_edge_s0
Launch Clk | main_rx_1_inst/aes3_bclk:[R]
Latch Clk | main_rx_1_inst/aes3_bclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R5C42[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
1.319 | 1.319 | tNET | RR | 1 | R23C38[1][B] | main_rx_1_inst/clocks/zzbsync_s0/CLK
1.652 | 0.333 | tC2Q | RR | 2 | R23C38[1][B] | main_rx_1_inst/clocks/zzbsync_s0/Q
1.890 | 0.238 | tNET | RR | 1 | R23C38[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | main_rx_1_inst/aes3_bclk
0.000 | 0.000 | tCL | RR | 38 | R5C42[1][A] | main_rx_1_inst/receiver/sclk_s0/Q
1.319 | 1.319 | tNET | RR | 1 | R23C38[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0/CLK
1.332 | 0.012 | tHld |  | 1 | R23C38[0][A] | main_rx_1_inst/clocks/bsync_pos_edge_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.319, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.319, 100.000%

### Path9

Path Summary:

Slack | 0.561
Data Arrival Time | 3.187
Data Required Time | 2.626
From | main_rx_1_inst/receiver/aes3_clk_s0
To | main_rx_1_inst/receiver/decoder_shift_7_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R5C37[1][B] | main_rx_1_inst/receiver/aes3_clk_s0/CLK
2.947 | 0.333 | tC2Q | RR | 18 | R5C37[1][B] | main_rx_1_inst/receiver/aes3_clk_s0/Q
3.187 | 0.240 | tNET | RR | 1 | R5C37[2][A] | main_rx_1_inst/receiver/decoder_shift_7_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R5C37[2][A] | main_rx_1_inst/receiver/decoder_shift_7_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R5C37[2][A] | main_rx_1_inst/receiver/decoder_shift_7_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path10

Path Summary:

Slack | 0.565
Data Arrival Time | 3.191
Data Required Time | 2.626
From | main_rx_1_inst/clocks/zzaes_lrclk_s0
To | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R21C34[1][A] | main_rx_1_inst/clocks/zzaes_lrclk_s0/CLK
2.947 | 0.333 | tC2Q | RR | 3 | R21C34[1][A] | main_rx_1_inst/clocks/zzaes_lrclk_s0/Q
3.191 | 0.244 | tNET | RR | 1 | R21C34[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk
2.429 | 2.429 | tCL | RR | 531 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD
2.614 | 0.185 | tNET | RR | 1 | R21C34[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/CLK
2.626 | 0.012 | tHld |  | 1 | R21C34[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.244, 42.242%; tC2Q: 0.333, 57.758%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path11

Path Summary:

Slack | 0.567
Data Arrival Time | 3.251
Data Required Time | 2.684
From | main_tx_inst/deserializer/bsync_pos_edge_s0
To | main_tx_inst/deserializer/new_data_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
3.005 | 0.333 | tC2Q | RR | 20 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q
3.251 | 0.246 | tNET | RR | 1 | R22C29[1][B] | main_tx_inst/deserializer/new_data_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C29[1][B] | main_tx_inst/deserializer/new_data_s0/CLK
2.684 | 0.012 | tHld |  | 1 | R22C29[1][B] | main_tx_inst/deserializer/new_data_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.246, 42.446%; tC2Q: 0.333, 57.554%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path12

Path Summary:

Slack | 0.590
Data Arrival Time | 3.274
Data Required Time | 2.684
From | main_tx_inst/deserializer/zzbsync_s0
To | main_tx_inst/deserializer/bsync_pos_edge_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C31[0][B] | main_tx_inst/deserializer/zzbsync_s0/CLK
3.005 | 0.333 | tC2Q | RR | 2 | R22C31[0][B] | main_tx_inst/deserializer/zzbsync_s0/Q
3.274 | 0.269 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK
2.684 | 0.012 | tHld |  | 1 | R22C29[0][B] | main_tx_inst/deserializer/bsync_pos_edge_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 44.630%; tC2Q: 0.333, 55.370%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path13

Path Summary:

Slack | 0.595
Data Arrival Time | 3.280
Data Required Time | 2.684
From | main_tx_inst2/serializer/aes_lrck_edge_s0
To | main_tx_inst2/serializer/ch_out_1_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R6C10[0][B] | main_tx_inst2/serializer/aes_lrck_edge_s0/CLK
3.005 | 0.333 | tC2Q | RR | 28 | R6C10[0][B] | main_tx_inst2/serializer/aes_lrck_edge_s0/Q
3.280 | 0.274 | tNET | RR | 1 | R6C11[1][A] | main_tx_inst2/serializer/ch_out_1_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R6C11[1][A] | main_tx_inst2/serializer/ch_out_1_s0/CLK
2.684 | 0.012 | tHld |  | 1 | R6C11[1][A] | main_tx_inst2/serializer/ch_out_1_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 45.149%; tC2Q: 0.333, 54.851%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path14

Path Summary:

Slack | 0.599
Data Arrival Time | 3.283
Data Required Time | 2.684
From | main_tx_inst2/serializer/aes_lrck_edge_s0
To | main_tx_inst2/serializer/ch_out_4_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R6C10[0][B] | main_tx_inst2/serializer/aes_lrck_edge_s0/CLK
3.005 | 0.333 | tC2Q | RR | 28 | R6C10[0][B] | main_tx_inst2/serializer/aes_lrck_edge_s0/Q
3.283 | 0.278 | tNET | RR | 1 | R6C12[2][B] | main_tx_inst2/serializer/ch_out_4_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R6C12[2][B] | main_tx_inst2/serializer/ch_out_4_s0/CLK
2.684 | 0.012 | tHld |  | 1 | R6C12[2][B] | main_tx_inst2/serializer/ch_out_4_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 45.486%; tC2Q: 0.333, 54.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path15

Path Summary:

Slack | 0.603
Data Arrival Time | 3.287
Data Required Time | 2.684
From | main_tx_inst2/serializer/aes_lrck_edge_s0
To | main_tx_inst2/serializer/ch_out_7_s0
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R6C10[0][B] | main_tx_inst2/serializer/aes_lrck_edge_s0/CLK
3.005 | 0.333 | tC2Q | RR | 28 | R6C10[0][B] | main_tx_inst2/serializer/aes_lrck_edge_s0/Q
3.287 | 0.282 | tNET | RR | 1 | R6C8[2][B] | main_tx_inst2/serializer/ch_out_7_s0/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R6C8[2][B] | main_tx_inst2/serializer/ch_out_7_s0/CLK
2.684 | 0.012 | tHld |  | 1 | R6C8[2][B] | main_tx_inst2/serializer/ch_out_7_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.282, 45.818%; tC2Q: 0.333, 54.182%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path16

Path Summary:

Slack | 0.708
Data Arrival Time | 3.380
Data Required Time | 2.672
From | main_tx_inst/deserializer/bit_cnt_4_s4
To | main_tx_inst/deserializer/bit_cnt_4_s4
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C32[1][A] | main_tx_inst/deserializer/bit_cnt_4_s4/CLK
3.005 | 0.333 | tC2Q | RR | 4 | R22C32[1][A] | main_tx_inst/deserializer/bit_cnt_4_s4/Q
3.008 | 0.002 | tNET | RR | 1 | R22C32[1][A] | main_tx_inst/deserializer/n44_s3/I0
3.380 | 0.372 | tINS | RF | 1 | R22C32[1][A] | main_tx_inst/deserializer/n44_s3/F
3.380 | 0.000 | tNET | FF | 1 | R22C32[1][A] | main_tx_inst/deserializer/bit_cnt_4_s4/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R22C32[1][A] | main_tx_inst/deserializer/bit_cnt_4_s4/CLK
2.672 | 0.000 | tHld |  | 1 | R22C32[1][A] | main_tx_inst/deserializer/bit_cnt_4_s4

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path17

Path Summary:

Slack | 0.708
Data Arrival Time | 3.380
Data Required Time | 2.672
From | main_tx_inst/deserializer/lrck_neg_edge_s4
To | main_tx_inst/deserializer/lrck_neg_edge_s4
Launch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/CLK
3.005 | 0.333 | tC2Q | RR | 2 | R16C26[1][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/Q
3.008 | 0.002 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/deserializer/n30_s2/I0
3.380 | 0.372 | tINS | RF | 1 | R16C26[1][A] | main_tx_inst/deserializer/n30_s2/F
3.380 | 0.000 | tNET | FF | 1 | R16C26[1][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
2.487 | 2.487 | tCL | RR | 1164 | PLL_R | pll_main_clock/rpll_inst/CLKOUT
2.672 | 0.185 | tNET | RR | 1 | R16C26[1][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/CLK
2.672 | 0.000 | tHld |  | 1 | R16C26[1][A] | main_tx_inst/deserializer/lrck_neg_edge_s4

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000%

### Path18

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/transmitter/data_biphase_s1
To | main_tx_inst2/transmitter/data_biphase_s1
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R11C17[0][A] | main_tx_inst2/transmitter/data_biphase_s1/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R11C17[0][A] | main_tx_inst2/transmitter/data_biphase_s1/Q
1.912 | 0.002 | tNET | RR | 1 | R11C17[0][A] | main_tx_inst2/transmitter/n2535_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R11C17[0][A] | main_tx_inst2/transmitter/n2535_s2/F
2.284 | 0.000 | tNET | FF | 1 | R11C17[0][A] | main_tx_inst2/transmitter/data_biphase_s1/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R11C17[0][A] | main_tx_inst2/transmitter/data_biphase_s1/CLK
1.577 | 0.000 | tHld |  | 1 | R11C17[0][A] | main_tx_inst2/transmitter/data_biphase_s1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path19

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/clocks/aes_lrclk_s2
To | main_tx_inst2/clocks/aes_lrclk_s2
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R15C16[0][A] | main_tx_inst2/clocks/aes_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R15C16[0][A] | main_tx_inst2/clocks/aes_lrclk_s2/Q
1.912 | 0.002 | tNET | RR | 1 | R15C16[0][A] | main_tx_inst2/clocks/n264_s3/I0
2.284 | 0.372 | tINS | RF | 1 | R15C16[0][A] | main_tx_inst2/clocks/n264_s3/F
2.284 | 0.000 | tNET | FF | 1 | R15C16[0][A] | main_tx_inst2/clocks/aes_lrclk_s2/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R15C16[0][A] | main_tx_inst2/clocks/aes_lrclk_s2/CLK
1.577 | 0.000 | tHld |  | 1 | R15C16[0][A] | main_tx_inst2/clocks/aes_lrclk_s2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path20

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/clocks/i2s_bclk_s2
To | main_tx_inst2/clocks/i2s_bclk_s2
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2/Q
1.912 | 0.002 | tNET | RR | 1 | R23C16[0][A] | main_tx_inst2/clocks/n43_s3/I0
2.284 | 0.372 | tINS | RF | 1 | R23C16[0][A] | main_tx_inst2/clocks/n43_s3/F
2.284 | 0.000 | tNET | FF | 1 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2/CLK
1.577 | 0.000 | tHld |  | 1 | R23C16[0][A] | main_tx_inst2/clocks/i2s_bclk_s2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path21

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/clocks/count_aes_lrclk_0_s0
To | main_tx_inst2/clocks/count_aes_lrclk_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R15C17[0][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R15C17[0][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/Q
1.912 | 0.002 | tNET | RR | 1 | R15C17[0][A] | main_tx_inst2/clocks/n255_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R15C17[0][A] | main_tx_inst2/clocks/n255_s2/F
2.284 | 0.000 | tNET | FF | 1 | R15C17[0][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R15C17[0][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R15C17[0][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path22

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/clocks/count_i2s_lrclk_0_s0
To | main_tx_inst2/clocks/count_i2s_lrclk_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R18C17[0][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R18C17[0][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/Q
1.912 | 0.002 | tNET | RR | 1 | R18C17[0][A] | main_tx_inst2/clocks/n143_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R18C17[0][A] | main_tx_inst2/clocks/n143_s2/F
2.284 | 0.000 | tNET | FF | 1 | R18C17[0][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R18C17[0][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R18C17[0][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path23

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst2/clocks/count_i2s_bclk_0_s0
To | main_tx_inst2/clocks/count_i2s_bclk_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C17[0][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R23C17[0][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/Q
1.912 | 0.002 | tNET | RR | 1 | R23C17[0][A] | main_tx_inst2/clocks/n38_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R23C17[0][A] | main_tx_inst2/clocks/n38_s2/F
2.284 | 0.000 | tNET | FF | 1 | R23C17[0][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C17[0][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R23C17[0][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path24

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst/clocks/aes_lrclk_s2
To | main_tx_inst/clocks/aes_lrclk_s2
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/CLK
1.910 | 0.333 | tC2Q | RR | 2 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/Q
1.912 | 0.002 | tNET | RR | 1 | R23C26[1][A] | main_tx_inst/clocks/n264_s3/I0
2.284 | 0.372 | tINS | RF | 1 | R23C26[1][A] | main_tx_inst/clocks/n264_s3/F
2.284 | 0.000 | tNET | FF | 1 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2/CLK
1.577 | 0.000 | tHld |  | 1 | R23C26[1][A] | main_tx_inst/clocks/aes_lrclk_s2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Path25

Path Summary:

Slack | 0.708
Data Arrival Time | 2.284
Data Required Time | 1.577
From | main_tx_inst/clocks/count_aes_lrclk_0_s0
To | main_tx_inst/clocks/count_aes_lrclk_0_s0
Launch Clk | i2s_in_sclk:[R]
Latch Clk | i2s_in_sclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C26[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/CLK
1.910 | 0.333 | tC2Q | RR | 3 | R23C26[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/Q
1.912 | 0.002 | tNET | RR | 1 | R23C26[0][A] | main_tx_inst/clocks/n255_s2/I0
2.284 | 0.372 | tINS | RF | 1 | R23C26[0][A] | main_tx_inst/clocks/n255_s2/F
2.284 | 0.000 | tNET | FF | 1 | R23C26[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | i2s_in_sclk
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | i2s_in_sclk_ibuf/I
1.392 | 1.392 | tINS | RR | 420 | IOB29[A] | i2s_in_sclk_ibuf/O
1.577 | 0.185 | tNET | RR | 1 | R23C26[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/CLK
1.577 | 0.000 | tHld |  | 1 | R23C26[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/zzbsync_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/zzbsync_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/zzbsync_s0/CLK

### MPW2

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/zzzbsync_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/zzzbsync_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/zzzbsync_s0/CLK

### MPW3

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_1_r_9_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_1_r_9_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_1_r_9_s0/CLK

### MPW4

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_r_21_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_r_21_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_r_21_s0/CLK

### MPW5

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_3_r_5_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_3_r_5_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_3_r_5_s0/CLK

### MPW6

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_4_r_19_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_4_r_19_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_4_r_19_s0/CLK

### MPW7

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_4_r_15_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_4_r_15_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_4_r_15_s0/CLK

### MPW8

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_4_r_13_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_4_r_13_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_4_r_13_s0/CLK

### MPW9

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst/deserializer/sample_out_ch_4_r_12_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst/deserializer/sample_out_ch_4_r_12_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst/deserializer/sample_out_ch_4_r_12_s0/CLK

### MPW10

MPW Summary:

Slack: | 0.707
Actual Width: | 1.957
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
Objects: | main_tx_inst2/deserializer/sample_out_ch_1_r_15_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.035 | 0.000 |  |  | active clock edge time
2.035 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
4.522 | 2.487 | tCL | FF | pll_main_clock/rpll_inst/CLKOUT
4.784 | 0.262 | tNET | FF | main_tx_inst2/deserializer/sample_out_ch_1_r_15_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
4.069 | 0.000 |  |  | active clock edge time
4.069 | 0.000 |  |  | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk
6.556 | 2.487 | tCL | RR | pll_main_clock/rpll_inst/CLKOUT
6.741 | 0.185 | tNET | RR | main_tx_inst2/deserializer/sample_out_ch_1_r_15_s0/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
1164 | clock_200M | -1.826 | 0.262
531 | clock_100M | -1.657 | 0.262
420 | i2s_in_sclk_d | -1.532 | 0.262
192 | n1680_3 | 1.044 | 3.112
180 | new_data_pos_edge | 0.036 | 2.143
180 | new_data_pos_edge | -0.458 | 3.063
162 | n175_8 | 27.308 | 3.793
101 | bit_counter[0] | -1.657 | 2.632
90 | n96_6 | 28.691 | 2.810
88 | n1658_4 | -1.453 | 2.298

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R8C8 | 94.44%
R14C37 | 91.67%
R11C24 | 90.28%
R14C36 | 86.11%
R12C36 | 86.11%
R6C9 | 84.72%
R11C10 | 84.72%
R15C37 | 83.33%
R16C39 | 83.33%
R9C12 | 83.33%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---