<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="src/gowin_rpll/gowin_rpll_245.v.v" type="file.verilog" enable="1"/>
        <File path="src/main.v" type="file.verilog" enable="1"/>
        <File path="src/main_rx.v" type="file.verilog" enable="1"/>
        <File path="src/main_tx.v" type="file.verilog" enable="1"/>
        <File path="src/aes3rx.vhd" type="file.vhdl" enable="1"/>
        <File path="src/aes3tx.vhd" type="file.vhdl" enable="1"/>
        <File path="src/i2s_deser.vhd" type="file.vhdl" enable="1"/>
        <File path="src/i2s_quad_deserializer.vhd" type="file.vhdl" enable="1"/>
        <File path="src/i2s_quad_transmitter.vhd" type="file.vhdl" enable="1"/>
        <File path="src/spdif_transmitter.vhd" type="file.vhdl" enable="1"/>
        <File path="src/ultranet_rx_clocks.vhd" type="file.vhdl" enable="1"/>
        <File path="src/ultranet_rx_demux.vhd" type="file.vhdl" enable="1"/>
        <File path="src/ultranet_rx_deserializer.vhd" type="file.vhdl" enable="1"/>
        <File path="src/ultranet_serializer.vhd" type="file.vhdl" enable="1"/>
        <File path="src/ultranet_tx_clocks.vhd" type="file.vhdl" enable="1"/>
        <File path="src/main.cst" type="file.cst" enable="1"/>
        <File path="src/test_fpga_project.sdc" type="file.sdc" enable="1"/>
    </FileList>
</Project>
