From 6a8e9843bbc21e6cf00318d79e8fc9a9a08087d1 Mon Sep 17 00:00:00 2001 From: TheStaticTurtle Date: Wed, 20 Aug 2025 22:34:26 +0200 Subject: [PATCH] Moved code used for the v1 prototype --- .../impl/gwsynthesis/test_fpga_project.log | 0 .../impl/gwsynthesis/test_fpga_project.prj | 0 .../impl/gwsynthesis/test_fpga_project.vg | 0 .../impl/gwsynthesis/test_fpga_project_syn.rpt.html | 0 .../gwsynthesis/test_fpga_project_syn_resource.html | 0 .../impl/gwsynthesis/test_fpga_project_syn_rsc.xml | 0 src/hdl/{ => test_fpga_project}/impl/pnr/cmd.do | 0 src/hdl/{ => test_fpga_project}/impl/pnr/device.cfg | 0 .../impl/pnr/test_fpga_project.bin | Bin .../impl/pnr/test_fpga_project.binx | Bin .../impl/pnr/test_fpga_project.db | Bin .../impl/pnr/test_fpga_project.fs | 0 .../impl/pnr/test_fpga_project.log | 0 .../impl/pnr/test_fpga_project.pin.html | 0 .../impl/pnr/test_fpga_project.power.html | 0 .../impl/pnr/test_fpga_project.rpt.html | 0 .../impl/pnr/test_fpga_project.rpt.txt | 0 .../impl/pnr/test_fpga_project.timing_paths | 0 .../impl/pnr/test_fpga_project.tr.html | 0 .../impl/pnr/test_fpga_project_tr_cata.html | 0 .../impl/pnr/test_fpga_project_tr_content.html | 0 .../impl/temp/rtl_parser.result | 0 .../impl/temp/rtl_parser_arg.json | 0 src/hdl/{ => test_fpga_project}/impl/temp/style.css | 0 .../impl/test_fpga_project_process_config.json | 0 src/hdl/{ => test_fpga_project}/src/aes3rx.vhd | 0 src/hdl/{ => test_fpga_project}/src/aes3tx.vhd | 0 .../src/gowin_rpll/gowin_rpll_245.v.v | 0 src/hdl/{ => test_fpga_project}/src/i2s_deser.vhd | 0 .../src/i2s_quad_deserializer.vhd | 0 .../src/i2s_quad_transmitter.vhd | 0 src/hdl/{ => test_fpga_project}/src/main.cst | 0 src/hdl/{ => test_fpga_project}/src/main.v | 0 src/hdl/{ => test_fpga_project}/src/main_rx.v | 0 src/hdl/{ => test_fpga_project}/src/main_tx.v | 0 .../src/spdif_transmitter.vhd | 0 .../src/test_fpga_project.sdc | 0 .../src/ultranet_rx_clocks.vhd | 0 .../src/ultranet_rx_demux.vhd | 0 .../src/ultranet_rx_deserializer.vhd | 0 .../src/ultranet_serializer.vhd | 0 .../src/ultranet_tx_clocks.vhd | 0 .../{ => test_fpga_project}/test_fpga_project.gprj | 0 .../test_fpga_project.gprj.user | 0 44 files changed, 0 insertions(+), 0 deletions(-) rename src/hdl/{ => test_fpga_project}/impl/gwsynthesis/test_fpga_project.log (100%) rename src/hdl/{ => test_fpga_project}/impl/gwsynthesis/test_fpga_project.prj (100%) rename src/hdl/{ => test_fpga_project}/impl/gwsynthesis/test_fpga_project.vg (100%) rename src/hdl/{ => test_fpga_project}/impl/gwsynthesis/test_fpga_project_syn.rpt.html (100%) rename src/hdl/{ => test_fpga_project}/impl/gwsynthesis/test_fpga_project_syn_resource.html (100%) rename src/hdl/{ => test_fpga_project}/impl/gwsynthesis/test_fpga_project_syn_rsc.xml (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/cmd.do (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/device.cfg (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.bin (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.binx (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.db (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.fs (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.log (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.pin.html (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.power.html (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.rpt.html (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.rpt.txt (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.timing_paths (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project.tr.html (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project_tr_cata.html (100%) rename src/hdl/{ => test_fpga_project}/impl/pnr/test_fpga_project_tr_content.html (100%) rename src/hdl/{ => test_fpga_project}/impl/temp/rtl_parser.result (100%) rename src/hdl/{ => test_fpga_project}/impl/temp/rtl_parser_arg.json (100%) rename src/hdl/{ => test_fpga_project}/impl/temp/style.css (100%) rename src/hdl/{ => test_fpga_project}/impl/test_fpga_project_process_config.json (100%) rename src/hdl/{ => test_fpga_project}/src/aes3rx.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/aes3tx.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/gowin_rpll/gowin_rpll_245.v.v (100%) rename src/hdl/{ => test_fpga_project}/src/i2s_deser.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/i2s_quad_deserializer.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/i2s_quad_transmitter.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/main.cst (100%) rename src/hdl/{ => test_fpga_project}/src/main.v (100%) rename src/hdl/{ => test_fpga_project}/src/main_rx.v (100%) rename src/hdl/{ => test_fpga_project}/src/main_tx.v (100%) rename src/hdl/{ => test_fpga_project}/src/spdif_transmitter.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/test_fpga_project.sdc (100%) rename src/hdl/{ => test_fpga_project}/src/ultranet_rx_clocks.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/ultranet_rx_demux.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/ultranet_rx_deserializer.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/ultranet_serializer.vhd (100%) rename src/hdl/{ => test_fpga_project}/src/ultranet_tx_clocks.vhd (100%) rename src/hdl/{ => test_fpga_project}/test_fpga_project.gprj (100%) rename src/hdl/{ => test_fpga_project}/test_fpga_project.gprj.user (100%) diff --git a/src/hdl/impl/gwsynthesis/test_fpga_project.log b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log similarity index 100% rename from src/hdl/impl/gwsynthesis/test_fpga_project.log rename to src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log diff --git a/src/hdl/impl/gwsynthesis/test_fpga_project.prj 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rename from src/hdl/impl/gwsynthesis/test_fpga_project_syn_resource.html rename to src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_resource.html diff --git a/src/hdl/impl/gwsynthesis/test_fpga_project_syn_rsc.xml b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_rsc.xml similarity index 100% rename from src/hdl/impl/gwsynthesis/test_fpga_project_syn_rsc.xml rename to src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_rsc.xml diff --git a/src/hdl/impl/pnr/cmd.do b/src/hdl/test_fpga_project/impl/pnr/cmd.do similarity index 100% rename from src/hdl/impl/pnr/cmd.do rename to src/hdl/test_fpga_project/impl/pnr/cmd.do diff --git a/src/hdl/impl/pnr/device.cfg b/src/hdl/test_fpga_project/impl/pnr/device.cfg similarity index 100% rename from src/hdl/impl/pnr/device.cfg rename to src/hdl/test_fpga_project/impl/pnr/device.cfg diff --git a/src/hdl/impl/pnr/test_fpga_project.bin b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.bin similarity 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similarity index 100% rename from src/hdl/src/main.v rename to src/hdl/test_fpga_project/src/main.v diff --git a/src/hdl/src/main_rx.v b/src/hdl/test_fpga_project/src/main_rx.v similarity index 100% rename from src/hdl/src/main_rx.v rename to src/hdl/test_fpga_project/src/main_rx.v diff --git a/src/hdl/src/main_tx.v b/src/hdl/test_fpga_project/src/main_tx.v similarity index 100% rename from src/hdl/src/main_tx.v rename to src/hdl/test_fpga_project/src/main_tx.v diff --git a/src/hdl/src/spdif_transmitter.vhd b/src/hdl/test_fpga_project/src/spdif_transmitter.vhd similarity index 100% rename from src/hdl/src/spdif_transmitter.vhd rename to src/hdl/test_fpga_project/src/spdif_transmitter.vhd diff --git a/src/hdl/src/test_fpga_project.sdc b/src/hdl/test_fpga_project/src/test_fpga_project.sdc similarity index 100% rename from src/hdl/src/test_fpga_project.sdc rename to src/hdl/test_fpga_project/src/test_fpga_project.sdc diff --git a/src/hdl/src/ultranet_rx_clocks.vhd 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