| Total Power (mW) | -37.476 | +37.498 | ||||
| Quiescent Power (mW) | @@ -169,7 +169,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }||||||
| Dynamic Power (mW) | -10.941 | +10.963 | ||||
| Psram Power (mW) | @@ -203,9 +203,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }||||||
| VCC | 1.200 | -6.911 | +6.930 | 3.507 | -12.503 | +12.525 |
| VCCX | @@ -240,9 +240,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }||||||
| Logic | -0.916 | +0.940 | NA | -17.883 | +17.770 | |
| IO | @@ -266,32 +266,32 @@ table.detail_table th.label { min-width: 8%; width: 8%; }||||||
| top | -7.771 | -7.771(7.771) | +7.795 | +7.795(7.795) | ||
| top/main_rx_1_inst/ | -0.226 | -0.226(0.226) | +0.250 | +0.250(0.250) | ||
| top/main_rx_1_inst/clocks/ | -0.065 | -0.065(0.000) | +0.064 | +0.064(0.000) | ||
| top/main_rx_1_inst/demuxer/ | -0.037 | -0.037(0.000) | +0.067 | +0.067(0.000) | ||
| top/main_rx_1_inst/deserializer/ | -0.015 | -0.015(0.000) | +0.013 | +0.013(0.000) | ||
| top/main_rx_1_inst/receiver/ | 0.035 | 0.035(0.000) | ||||
| top/main_rx_1_inst/transmitter/ | -0.075 | -0.075(0.000) | +0.071 | +0.071(0.000) | ||
| top/main_tx_inst/ | 0.345 | @@ -345,19 +345,19 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Total Dynamic Power(mW) | ||||
|---|---|---|---|---|---|---|
| i2s_in_sclk | -24.576 | -6.987 | -||||
| NO CLOCK DOMAIN | 0.000 | 0.000 | ||||
| i2s_in_sclk | +24.576 | +6.987 | +||||
| pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | 122.880 | -0.198 | +0.220 | |||
| pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | diff --git a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html index ac03fd1..04b1307 100644 --- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html +++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html @@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }||||||
| Created Time | -Sat Oct 4 00:11:09 2025 + | Sat Oct 4 16:56:29 2025 | ||||
| Place & Route Process | Running placement: - Placement Phase 0: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.19s - Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.092s - Placement Phase 2: CPU time = 0h 0m 0.747s, Elapsed time = 0h 0m 0.748s + Placement Phase 0: CPU time = 0h 0m 0.204s, Elapsed time = 0h 0m 0.204s + Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.091s + Placement Phase 2: CPU time = 0h 0m 0.741s, Elapsed time = 0h 0m 0.741s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Running routing: Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s - Routing Phase 1: CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.561s - Routing Phase 2: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s + Routing Phase 1: CPU time = 0h 0m 0.615s, Elapsed time = 0h 0m 0.616s + Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s - Total Routing: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s + Total Routing: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s Generate output files: - CPU time = 0h 0m 0.766s, Elapsed time = 0h 0m 0.765s + CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.734s | |||||
| Total Time and Memory Usage | -CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 330MB | +CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 332MB |
| Slack | --1.826 | +-2.097 |
| Data Arrival Time | -8.226 | -|
| Data Required Time | -6.400 | -|
| From | -main_tx_inst/serializer/channel_cnt_0_s3 | -|
| To | -main_tx_inst/serializer/ch_out_6_s0 | -|
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -|
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/Q | -
| 4.498 | -1.308 | -tNET | -FF | -1 | -R12C22[0][B] | -main_tx_inst/serializer/n381_s12/I0 | -
| 5.124 | -0.626 | -tINS | -FF | -22 | -R12C22[0][B] | -main_tx_inst/serializer/n381_s12/F | -
| 7.265 | -2.142 | -tNET | -FF | -1 | -R9C28[3][A] | -main_tx_inst/serializer/n398_s13/I2 | -
| 7.890 | -0.625 | -tINS | -FR | -1 | -R9C28[3][A] | -main_tx_inst/serializer/n398_s13/F | -
| 7.890 | -0.000 | -tNET | -RR | -1 | -R9C28[3][A] | -main_tx_inst/serializer/n398_s9/I0 | -
| 8.040 | -0.150 | -tINS | -RR | -1 | -R9C28[3][A] | -main_tx_inst/serializer/n398_s9/O | -
| 8.040 | -0.000 | -tNET | -RR | -1 | -R9C28[2][B] | -main_tx_inst/serializer/n398_s5/I0 | -
| 8.217 | -0.177 | -tINS | -RR | -1 | -R9C28[2][B] | -main_tx_inst/serializer/n398_s5/O | -
| 8.226 | -0.009 | -tNET | -RR | -1 | -R9C28[2][B] | -main_tx_inst/serializer/ch_out_6_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R9C28[2][B] | -main_tx_inst/serializer/ch_out_6_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R9C28[2][B] | -main_tx_inst/serializer/ch_out_6_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 1.578, 28.717%; route: 3.459, 62.943%; tC2Q: 0.458, 8.341% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.817 | -
| Data Arrival Time | -8.218 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_2_s1 | -
| To | -main_tx_inst2/serializer/ch_out_4_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -30 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/Q | -
| 4.380 | -1.191 | -tNET | -FF | -1 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/I1 | -
| 5.412 | -1.032 | -tINS | -FF | -22 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/F | -
| 7.257 | -1.845 | -tNET | -FF | -1 | -R6C12[3][B] | -main_tx_inst2/serializer/n400_s14/I2 | -
| 7.882 | -0.625 | -tINS | -FR | -1 | -R6C12[3][B] | -main_tx_inst2/serializer/n400_s14/F | -
| 7.882 | -0.000 | -tNET | -RR | -1 | -R6C12[3][A] | -main_tx_inst2/serializer/n400_s9/I1 | -
| 8.032 | -0.150 | -tINS | -RR | -1 | -R6C12[3][A] | -main_tx_inst2/serializer/n400_s9/O | -
| 8.032 | -0.000 | -tNET | -RR | -1 | -R6C12[2][B] | -main_tx_inst2/serializer/n400_s5/I0 | -
| 8.209 | -0.177 | -tINS | -RR | -1 | -R6C12[2][B] | -main_tx_inst2/serializer/n400_s5/O | -
| 8.218 | -0.009 | -tNET | -RR | -1 | -R6C12[2][B] | -main_tx_inst2/serializer/ch_out_4_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R6C12[2][B] | -main_tx_inst2/serializer/ch_out_4_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R6C12[2][B] | -main_tx_inst2/serializer/ch_out_4_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 1.984, 36.162%; route: 3.044, 55.484%; tC2Q: 0.458, 8.354% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.807 | -
| Data Arrival Time | -8.207 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_2_s1 | -
| To | -main_tx_inst2/serializer/ch_out_19_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -30 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/Q | -
| 4.380 | -1.191 | -tNET | -FF | -1 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/I1 | -
| 5.412 | -1.032 | -tINS | -FF | -22 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/F | -
| 7.246 | -1.834 | -tNET | -FF | -1 | -R12C11[3][B] | -main_tx_inst2/serializer/n385_s14/I2 | -
| 7.871 | -0.625 | -tINS | -FR | -1 | -R12C11[3][B] | -main_tx_inst2/serializer/n385_s14/F | -
| 7.871 | -0.000 | -tNET | -RR | -1 | -R12C11[3][A] | -main_tx_inst2/serializer/n385_s9/I1 | -
| 8.021 | -0.150 | -tINS | -RR | -1 | -R12C11[3][A] | -main_tx_inst2/serializer/n385_s9/O | -
| 8.021 | -0.000 | -tNET | -RR | -1 | -R12C11[2][B] | -main_tx_inst2/serializer/n385_s5/I0 | -
| 8.198 | -0.177 | -tINS | -RR | -1 | -R12C11[2][B] | -main_tx_inst2/serializer/n385_s5/O | -
| 8.207 | -0.009 | -tNET | -RR | -1 | -R12C11[2][B] | -main_tx_inst2/serializer/ch_out_19_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R12C11[2][B] | -main_tx_inst2/serializer/ch_out_19_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R12C11[2][B] | -main_tx_inst2/serializer/ch_out_19_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 1.984, 36.233%; route: 3.033, 55.397%; tC2Q: 0.458, 8.370% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.803 | -
| Data Arrival Time | -8.203 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_2_s1 | -
| To | -main_tx_inst2/serializer/ch_out_2_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -30 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/Q | -
| 4.380 | -1.191 | -tNET | -FF | -1 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/I1 | -
| 5.412 | -1.032 | -tINS | -FF | -22 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/F | -
| 6.777 | -1.365 | -tNET | -FF | -1 | -R6C7[3][B] | -main_tx_inst2/serializer/n402_s14/I2 | -
| 7.876 | -1.099 | -tINS | -FF | -1 | -R6C7[3][B] | -main_tx_inst2/serializer/n402_s14/F | -
| 7.876 | -0.000 | -tNET | -FF | -1 | -R6C7[3][A] | -main_tx_inst2/serializer/n402_s9/I1 | -
| 8.025 | -0.149 | -tINS | -FF | -1 | -R6C7[3][A] | -main_tx_inst2/serializer/n402_s9/O | -
| 8.025 | -0.000 | -tNET | -FF | -1 | -R6C7[2][B] | -main_tx_inst2/serializer/n402_s5/I0 | -
| 8.188 | -0.163 | -tINS | -FF | -1 | -R6C7[2][B] | -main_tx_inst2/serializer/n402_s5/O | -
| 8.203 | -0.015 | -tNET | -FF | -1 | -R6C7[2][B] | -main_tx_inst2/serializer/ch_out_2_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R6C7[2][B] | -main_tx_inst2/serializer/ch_out_2_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R6C7[2][B] | -main_tx_inst2/serializer/ch_out_2_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.443, 44.644%; route: 2.571, 46.980%; tC2Q: 0.458, 8.376% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.800 | -
| Data Arrival Time | -8.557 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.557 | -1.645 | -tNET | -RR | -1 | -R9C5[2][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R9C5[2][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R9C5[2][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_23_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.729%; route: 4.742, 81.403%; tC2Q: 0.458, 7.868% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.799 | -
| Data Arrival Time | -8.199 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_2_s1 | -
| To | -main_tx_inst2/serializer/ch_out_12_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -30 | -R8C10[2][A] | -main_tx_inst2/serializer/channel_cnt_2_s1/Q | -
| 4.380 | -1.191 | -tNET | -FF | -1 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/I1 | -
| 5.412 | -1.032 | -tINS | -FF | -22 | -R9C8[3][B] | -main_tx_inst2/serializer/n333_s6/F | -
| 6.773 | -1.361 | -tNET | -FF | -1 | -R12C7[3][B] | -main_tx_inst2/serializer/n392_s14/I2 | -
| 7.872 | -1.099 | -tINS | -FF | -1 | -R12C7[3][B] | -main_tx_inst2/serializer/n392_s14/F | -
| 7.872 | -0.000 | -tNET | -FF | -1 | -R12C7[3][A] | -main_tx_inst2/serializer/n392_s9/I1 | -
| 8.021 | -0.149 | -tINS | -FF | -1 | -R12C7[3][A] | -main_tx_inst2/serializer/n392_s9/O | -
| 8.021 | -0.000 | -tNET | -FF | -1 | -R12C7[2][B] | -main_tx_inst2/serializer/n392_s5/I0 | -
| 8.184 | -0.163 | -tINS | -FF | -1 | -R12C7[2][B] | -main_tx_inst2/serializer/n392_s5/O | -
| 8.199 | -0.015 | -tNET | -FF | -1 | -R12C7[2][B] | -main_tx_inst2/serializer/ch_out_12_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R12C7[2][B] | -main_tx_inst2/serializer/ch_out_12_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R12C7[2][B] | -main_tx_inst2/serializer/ch_out_12_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.443, 44.681%; route: 2.566, 46.936%; tC2Q: 0.458, 8.383% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.796 | -
| Data Arrival Time | -8.553 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.553 | -1.641 | -tNET | -RR | -1 | -R8C14[2][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R8C14[2][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R8C14[2][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_20_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.736%; route: 4.738, 81.391%; tC2Q: 0.458, 7.873% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.792 | -
| Data Arrival Time | -8.192 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst/serializer/ch_out_3_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/Q | -
| 4.018 | -0.828 | -tNET | -FF | -1 | -R11C22[1][A] | -main_tx_inst/serializer/n237_s2/I0 | -
| 5.050 | -1.032 | -tINS | -FF | -22 | -R11C22[1][A] | -main_tx_inst/serializer/n237_s2/F | -
| 7.043 | -1.993 | -tNET | -FF | -1 | -R8C28[2][B] | -main_tx_inst/serializer/n401_s12/I2 | -
| 7.865 | -0.822 | -tINS | -FF | -1 | -R8C28[2][B] | -main_tx_inst/serializer/n401_s12/F | -
| 7.865 | -0.000 | -tNET | -FF | -1 | -R8C28[2][A] | -main_tx_inst/serializer/n401_s10/I1 | -
| 8.014 | -0.149 | -tINS | -FF | -1 | -R8C28[2][A] | -main_tx_inst/serializer/n401_s10/O | -
| 8.014 | -0.000 | -tNET | -FF | -1 | -R8C28[2][B] | -main_tx_inst/serializer/n401_s5/I1 | -
| 8.177 | -0.163 | -tINS | -FF | -1 | -R8C28[2][B] | -main_tx_inst/serializer/n401_s5/O | -
| 8.192 | -0.015 | -tNET | -FF | -1 | -R8C28[2][B] | -main_tx_inst/serializer/ch_out_3_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R8C28[2][B] | -main_tx_inst/serializer/ch_out_3_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R8C28[2][B] | -main_tx_inst/serializer/ch_out_3_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.166, 39.666%; route: 2.836, 51.941%; tC2Q: 0.458, 8.393% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.764 | -||||||||
| Data Arrival Time | -8.521 | +8.854 | |||||||
| Data Required Time | @@ -3002,7 +1078,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R22C29[0][B] | +R22C30[0][A] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | |||
| tC2Q | RF | 20 | -R22C29[0][B] | +R22C30[0][A] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | ||||
| 6.287 | -3.097 | +6.618 | +3.428 | tNET | FF | 1 | -R15C10[1][A] | +R16C9[0][B] | main_tx_inst2/deserializer/n1844_s1/I0 |
| 6.912 | +7.243 | 0.625 | tINS | FR | 88 | -R15C10[1][A] | +R16C9[0][B] | main_tx_inst2/deserializer/n1844_s1/F | |
| 8.521 | -1.609 | +8.854 | +1.611 | tNET | RR | 1 | -R7C6[0][B] | +R11C12[0][A] | main_tx_inst2/deserializer/sample_out_ch_4_l_2_s0/CE |
Path Summary:
| Slack | --1.764 | +-2.097 |
| Data Arrival Time | -8.521 | -|
| Data Required Time | -6.757 | -|
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -|
| To | -main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0 | -|
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -|
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.521 | -1.609 | -tNET | -RR | -1 | -R7C6[0][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R7C6[0][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R7C6[0][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_4_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.794%; route: 4.707, 81.290%; tC2Q: 0.458, 7.916% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.761 | -
| Data Arrival Time | -8.162 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst/serializer/ch_out_11_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/Q | -
| 4.018 | -0.828 | -tNET | -FF | -1 | -R11C22[1][A] | -main_tx_inst/serializer/n237_s2/I0 | -
| 5.050 | -1.032 | -tINS | -FF | -22 | -R11C22[1][A] | -main_tx_inst/serializer/n237_s2/F | -
| 6.736 | -1.686 | -tNET | -FF | -1 | -R13C28[2][B] | -main_tx_inst/serializer/n393_s12/I2 | -
| 7.835 | -1.099 | -tINS | -FF | -1 | -R13C28[2][B] | -main_tx_inst/serializer/n393_s12/F | -
| 7.835 | -0.000 | -tNET | -FF | -1 | -R13C28[2][A] | -main_tx_inst/serializer/n393_s10/I1 | -
| 7.984 | -0.149 | -tINS | -FF | -1 | -R13C28[2][A] | -main_tx_inst/serializer/n393_s10/O | -
| 7.984 | -0.000 | -tNET | -FF | -1 | -R13C28[2][B] | -main_tx_inst/serializer/n393_s5/I1 | -
| 8.147 | -0.163 | -tINS | -FF | -1 | -R13C28[2][B] | -main_tx_inst/serializer/n393_s5/O | -
| 8.162 | -0.015 | -tNET | -FF | -1 | -R13C28[2][B] | -main_tx_inst/serializer/ch_out_11_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R13C28[2][B] | -main_tx_inst/serializer/ch_out_11_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R13C28[2][B] | -main_tx_inst/serializer/ch_out_11_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.443, 44.988%; route: 2.529, 46.572%; tC2Q: 0.458, 8.440% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.752 | -
| Data Arrival Time | -8.509 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.509 | -1.597 | -tNET | -RR | -1 | -R12C5[0][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R12C5[0][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R12C5[0][A] | -main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.818%; route: 4.694, 81.249%; tC2Q: 0.458, 7.933% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.748 | -
| Data Arrival Time | -8.505 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.505 | -1.593 | -tNET | -RR | -1 | -R7C14[1][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R7C14[1][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R7C14[1][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.825%; route: 4.690, 81.236%; tC2Q: 0.458, 7.938% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.745 | -
| Data Arrival Time | -8.502 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.502 | -1.590 | -tNET | -RR | -1 | -R11C13[0][B] | -main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R11C13[0][B] | -main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R11C13[0][B] | -main_tx_inst2/deserializer/sample_out_ch_3_l_4_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.831%; route: 4.687, 81.226%; tC2Q: 0.458, 7.943% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.745 | -
| Data Arrival Time | -8.502 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.502 | -1.590 | -tNET | -RR | -1 | -R11C13[0][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R11C13[0][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R11C13[0][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_5_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.831%; route: 4.687, 81.226%; tC2Q: 0.458, 7.943% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.745 | -
| Data Arrival Time | -8.502 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.502 | -1.590 | -tNET | -RR | -1 | -R11C13[1][B] | -main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R11C13[1][B] | -main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R11C13[1][B] | -main_tx_inst2/deserializer/sample_out_ch_3_l_21_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.831%; route: 4.687, 81.226%; tC2Q: 0.458, 7.943% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.742 | -
| Data Arrival Time | -8.143 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst/serializer/ch_out_22_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/Q | -
| 4.498 | -1.308 | -tNET | -FF | -1 | -R12C22[0][B] | -main_tx_inst/serializer/n381_s12/I0 | -
| 5.124 | -0.626 | -tINS | -FF | -22 | -R12C22[0][B] | -main_tx_inst/serializer/n381_s12/F | -
| 6.781 | -1.657 | -tNET | -FF | -1 | -R11C28[3][A] | -main_tx_inst/serializer/n382_s13/I2 | -
| 7.807 | -1.026 | -tINS | -FR | -1 | -R11C28[3][A] | -main_tx_inst/serializer/n382_s13/F | -
| 7.807 | -0.000 | -tNET | -RR | -1 | -R11C28[3][A] | -main_tx_inst/serializer/n382_s9/I0 | -
| 7.957 | -0.150 | -tINS | -RR | -1 | -R11C28[3][A] | -main_tx_inst/serializer/n382_s9/O | -
| 7.957 | -0.000 | -tNET | -RR | -1 | -R11C28[2][B] | -main_tx_inst/serializer/n382_s5/I0 | -
| 8.134 | -0.177 | -tINS | -RR | -1 | -R11C28[2][B] | -main_tx_inst/serializer/n382_s5/O | -
| 8.143 | -0.009 | -tNET | -RR | -1 | -R11C28[2][B] | -main_tx_inst/serializer/ch_out_22_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R11C28[2][B] | -main_tx_inst/serializer/ch_out_22_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R11C28[2][B] | -main_tx_inst/serializer/ch_out_22_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 1.979, 36.570%; route: 2.974, 54.960%; tC2Q: 0.458, 8.470% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.719 | -
| Data Arrival Time | -8.119 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst/serializer/ch_out_8_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R9C21[0][A] | -main_tx_inst/serializer/channel_cnt_0_s3/Q | -
| 4.498 | -1.308 | -tNET | -FF | -1 | -R12C22[0][B] | -main_tx_inst/serializer/n381_s12/I0 | -
| 5.124 | -0.626 | -tINS | -FF | -22 | -R12C22[0][B] | -main_tx_inst/serializer/n381_s12/F | -
| 6.970 | -1.846 | -tNET | -FF | -1 | -R9C25[3][A] | -main_tx_inst/serializer/n396_s13/I2 | -
| 7.792 | -0.822 | -tINS | -FF | -1 | -R9C25[3][A] | -main_tx_inst/serializer/n396_s13/F | -
| 7.792 | -0.000 | -tNET | -FF | -1 | -R9C25[3][A] | -main_tx_inst/serializer/n396_s9/I0 | -
| 7.941 | -0.149 | -tINS | -FF | -1 | -R9C25[3][A] | -main_tx_inst/serializer/n396_s9/O | -
| 7.941 | -0.000 | -tNET | -FF | -1 | -R9C25[2][B] | -main_tx_inst/serializer/n396_s5/I0 | -
| 8.104 | -0.163 | -tINS | -FF | -1 | -R9C25[2][B] | -main_tx_inst/serializer/n396_s5/O | -
| 8.119 | -0.015 | -tNET | -FF | -1 | -R9C25[2][B] | -main_tx_inst/serializer/ch_out_8_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R9C25[2][B] | -main_tx_inst/serializer/ch_out_8_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R9C25[2][B] | -main_tx_inst/serializer/ch_out_8_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 1.760, 32.668%; route: 3.169, 58.825%; tC2Q: 0.458, 8.507% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.713 | -
| Data Arrival Time | -8.113 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst2/serializer/ch_out_14_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C11[1][A] | -main_tx_inst2/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R8C11[1][A] | -main_tx_inst2/serializer/channel_cnt_0_s3/Q | -
| 4.510 | -1.320 | -tNET | -FF | -1 | -R8C8[3][A] | -main_tx_inst2/serializer/n237_s2/I0 | -
| 5.332 | -0.822 | -tINS | -FF | -22 | -R8C8[3][A] | -main_tx_inst2/serializer/n237_s2/F | -
| 6.687 | -1.355 | -tNET | -FF | -1 | -R11C9[2][B] | -main_tx_inst2/serializer/n390_s12/I2 | -
| 7.786 | -1.099 | -tINS | -FF | -1 | -R11C9[2][B] | -main_tx_inst2/serializer/n390_s12/F | -
| 7.786 | -0.000 | -tNET | -FF | -1 | -R11C9[2][A] | -main_tx_inst2/serializer/n390_s10/I1 | -
| 7.935 | -0.149 | -tINS | -FF | -1 | -R11C9[2][A] | -main_tx_inst2/serializer/n390_s10/O | -
| 7.935 | -0.000 | -tNET | -FF | -1 | -R11C9[2][B] | -main_tx_inst2/serializer/n390_s5/I1 | -
| 8.098 | -0.163 | -tINS | -FF | -1 | -R11C9[2][B] | -main_tx_inst2/serializer/n390_s5/O | -
| 8.113 | -0.015 | -tNET | -FF | -1 | -R11C9[2][B] | -main_tx_inst2/serializer/ch_out_14_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R11C9[2][B] | -main_tx_inst2/serializer/ch_out_14_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R11C9[2][B] | -main_tx_inst2/serializer/ch_out_14_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.233, 41.489%; route: 2.691, 49.995%; tC2Q: 0.458, 8.516% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.713 | -
| Data Arrival Time | -8.113 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst2/serializer/ch_out_15_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C11[1][A] | -main_tx_inst2/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R8C11[1][A] | -main_tx_inst2/serializer/channel_cnt_0_s3/Q | -
| 4.510 | -1.320 | -tNET | -FF | -1 | -R8C8[3][A] | -main_tx_inst2/serializer/n237_s2/I0 | -
| 5.332 | -0.822 | -tINS | -FF | -22 | -R8C8[3][A] | -main_tx_inst2/serializer/n237_s2/F | -
| 6.687 | -1.355 | -tNET | -FF | -1 | -R9C6[2][B] | -main_tx_inst2/serializer/n389_s12/I2 | -
| 7.786 | -1.099 | -tINS | -FF | -1 | -R9C6[2][B] | -main_tx_inst2/serializer/n389_s12/F | -
| 7.786 | -0.000 | -tNET | -FF | -1 | -R9C6[2][A] | -main_tx_inst2/serializer/n389_s10/I1 | -
| 7.935 | -0.149 | -tINS | -FF | -1 | -R9C6[2][A] | -main_tx_inst2/serializer/n389_s10/O | -
| 7.935 | -0.000 | -tNET | -FF | -1 | -R9C6[2][B] | -main_tx_inst2/serializer/n389_s5/I1 | -
| 8.098 | -0.163 | -tINS | -FF | -1 | -R9C6[2][B] | -main_tx_inst2/serializer/n389_s5/O | -
| 8.113 | -0.015 | -tNET | -FF | -1 | -R9C6[2][B] | -main_tx_inst2/serializer/ch_out_15_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R9C6[2][B] | -main_tx_inst2/serializer/ch_out_15_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R9C6[2][B] | -main_tx_inst2/serializer/ch_out_15_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.233, 41.489%; route: 2.691, 49.995%; tC2Q: 0.458, 8.516% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.707 | -
| Data Arrival Time | -8.108 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_1_s3 | -
| To | -main_tx_inst2/serializer/ch_out_7_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C10[0][A] | -main_tx_inst2/serializer/channel_cnt_1_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -9 | -R8C10[0][A] | -main_tx_inst2/serializer/channel_cnt_1_s3/Q | -
| 4.009 | -0.819 | -tNET | -FF | -1 | -R9C11[1][B] | -main_tx_inst2/serializer/n285_s9/I1 | -
| 5.108 | -1.099 | -tINS | -FF | -22 | -R9C11[1][B] | -main_tx_inst2/serializer/n285_s9/F | -
| 6.959 | -1.851 | -tNET | -FF | -1 | -R6C8[2][A] | -main_tx_inst2/serializer/n397_s11/I2 | -
| 7.781 | -0.822 | -tINS | -FF | -1 | -R6C8[2][A] | -main_tx_inst2/serializer/n397_s11/F | -
| 7.781 | -0.000 | -tNET | -FF | -1 | -R6C8[2][A] | -main_tx_inst2/serializer/n397_s10/I0 | -
| 7.930 | -0.149 | -tINS | -FF | -1 | -R6C8[2][A] | -main_tx_inst2/serializer/n397_s10/O | -
| 7.930 | -0.000 | -tNET | -FF | -1 | -R6C8[2][B] | -main_tx_inst2/serializer/n397_s5/I1 | -
| 8.093 | -0.163 | -tINS | -FF | -1 | -R6C8[2][B] | -main_tx_inst2/serializer/n397_s5/O | -
| 8.108 | -0.015 | -tNET | -FF | -1 | -R6C8[2][B] | -main_tx_inst2/serializer/ch_out_7_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R6C8[2][B] | -main_tx_inst2/serializer/ch_out_7_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R6C8[2][B] | -main_tx_inst2/serializer/ch_out_7_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.233, 41.533%; route: 2.685, 49.942%; tC2Q: 0.458, 8.525% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.707 | -
| Data Arrival Time | -8.464 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.464 | -1.552 | -tNET | -RR | -1 | -R7C9[0][B] | -main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R7C9[0][B] | -main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R7C9[0][B] | -main_tx_inst2/deserializer/sample_out_ch_4_l_3_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.903%; route: 4.649, 81.102%; tC2Q: 0.458, 7.995% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.707 | -
| Data Arrival Time | -8.464 | -
| Data Required Time | -6.757 | -
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| To | -main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -20 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/Q | -
| 6.287 | -3.097 | -tNET | -FF | -1 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/I0 | -
| 6.912 | -0.625 | -tINS | -FR | -88 | -R15C10[1][A] | -main_tx_inst2/deserializer/n1844_s1/F | -
| 8.464 | -1.552 | -tNET | -RR | -1 | -R7C9[0][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R7C9[0][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0/CLK | -
| 6.757 | --0.043 | -tSu | -- | 1 | -R7C9[0][A] | -main_tx_inst2/deserializer/sample_out_ch_3_l_22_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 0.625, 10.903%; route: 4.649, 81.102%; tC2Q: 0.458, 7.995% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.702 | -
| Data Arrival Time | -8.102 | -
| Data Required Time | -6.400 | -
| From | -main_tx_inst2/serializer/channel_cnt_0_s3 | -
| To | -main_tx_inst2/serializer/ch_out_18_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.731 | -0.244 | -tNET | -RR | -1 | -R8C11[1][A] | -main_tx_inst2/serializer/channel_cnt_0_s3/CLK | -
| 3.190 | -0.458 | -tC2Q | -RF | -7 | -R8C11[1][A] | -main_tx_inst2/serializer/channel_cnt_0_s3/Q | -
| 4.510 | -1.320 | -tNET | -FF | -1 | -R8C8[3][A] | -main_tx_inst2/serializer/n237_s2/I0 | -
| 5.332 | -0.822 | -tINS | -FF | -22 | -R8C8[3][A] | -main_tx_inst2/serializer/n237_s2/F | -
| 6.676 | -1.344 | -tNET | -FF | -1 | -R9C11[2][B] | -main_tx_inst2/serializer/n386_s12/I2 | -
| 7.775 | -1.099 | -tINS | -FF | -1 | -R9C11[2][B] | -main_tx_inst2/serializer/n386_s12/F | -
| 7.775 | -0.000 | -tNET | -FF | -1 | -R9C11[2][A] | -main_tx_inst2/serializer/n386_s10/I1 | -
| 7.924 | -0.149 | -tINS | -FF | -1 | -R9C11[2][A] | -main_tx_inst2/serializer/n386_s10/O | -
| 7.924 | -0.000 | -tNET | -FF | -1 | -R9C11[2][B] | -main_tx_inst2/serializer/n386_s5/I1 | -
| 8.087 | -0.163 | -tINS | -FF | -1 | -R9C11[2][B] | -main_tx_inst2/serializer/n386_s5/O | -
| 8.102 | -0.015 | -tNET | -FF | -1 | -R9C11[2][B] | -main_tx_inst2/serializer/ch_out_18_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 4.069 | -4.069 | -- | - | - | - | active clock edge time | -
| 4.069 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 6.556 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 6.800 | -0.244 | -tNET | -RR | -1 | -R9C11[2][B] | -main_tx_inst2/serializer/ch_out_18_s0/CLK | -
| 6.400 | --0.400 | -tSu | -- | 1 | -R9C11[2][B] | -main_tx_inst2/serializer/ch_out_18_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Setup Relationship | -4.069 | -
| Logic Level | -3 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
| Arrival Data Path Delay | -cell: 2.233, 41.577%; route: 2.679, 49.889%; tC2Q: 0.458, 8.534% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.244, 100.000% | -
Path Summary:
-| Slack | --1.700 | -||||||||
| Data Arrival Time | -8.457 | +8.854 | |||||||
| Data Required Time | @@ -6580,7 +1278,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R22C29[0][B] | +R22C30[0][A] | main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | |||
| tC2Q | RF | 20 | -R22C29[0][B] | +R22C30[0][A] | main_tx_inst/deserializer/bsync_pos_edge_s0/Q | ||||
| 6.287 | -3.097 | +6.618 | +3.428 | tNET | FF | 1 | -R15C10[1][A] | +R16C9[0][B] | main_tx_inst2/deserializer/n1844_s1/I0 |
| 6.912 | +7.243 | 0.625 | tINS | FR | 88 | -R15C10[1][A] | +R16C9[0][B] | main_tx_inst2/deserializer/n1844_s1/F | |
| 8.457 | -1.545 | +8.854 | +1.611 | tNET | RR | 1 | -R9C13[1][A] | +R11C12[2][A] | main_tx_inst2/deserializer/sample_out_ch_4_l_21_s0/CE |
Path Summary:
+| Slack | +-2.097 | +
| Data Arrival Time | +8.854 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_3_l_9_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.854 | +1.611 | +tNET | +RR | +1 | +R11C12[2][B] | +main_tx_inst2/deserializer/sample_out_ch_3_l_9_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C12[2][B] | +main_tx_inst2/deserializer/sample_out_ch_3_l_9_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C12[2][B] | +main_tx_inst2/deserializer/sample_out_ch_3_l_9_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.208%; route: 5.039, 82.306%; tC2Q: 0.458, 7.486% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.097 | +
| Data Arrival Time | +8.854 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_1_l_20_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.854 | +1.611 | +tNET | +RR | +1 | +R11C12[0][B] | +main_tx_inst2/deserializer/sample_out_ch_1_l_20_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C12[0][B] | +main_tx_inst2/deserializer/sample_out_ch_1_l_20_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C12[0][B] | +main_tx_inst2/deserializer/sample_out_ch_1_l_20_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.208%; route: 5.039, 82.306%; tC2Q: 0.458, 7.486% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.092 | +
| Data Arrival Time | +8.849 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.849 | +1.607 | +tNET | +RR | +1 | +R11C13[1][A] | +main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C13[1][A] | +main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C13[1][A] | +main_tx_inst2/deserializer/sample_out_ch_3_l_2_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.216%; route: 5.035, 82.293%; tC2Q: 0.458, 7.492% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.088 | +
| Data Arrival Time | +8.845 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_4_l_7_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.845 | +1.602 | +tNET | +RR | +1 | +R11C6[1][A] | +main_tx_inst2/deserializer/sample_out_ch_4_l_7_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C6[1][A] | +main_tx_inst2/deserializer/sample_out_ch_4_l_7_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C6[1][A] | +main_tx_inst2/deserializer/sample_out_ch_4_l_7_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.223%; route: 5.030, 82.279%; tC2Q: 0.458, 7.497% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.088 | +
| Data Arrival Time | +8.845 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_4_l_8_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.845 | +1.602 | +tNET | +RR | +1 | +R11C6[1][B] | +main_tx_inst2/deserializer/sample_out_ch_4_l_8_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C6[1][B] | +main_tx_inst2/deserializer/sample_out_ch_4_l_8_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C6[1][B] | +main_tx_inst2/deserializer/sample_out_ch_4_l_8_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.223%; route: 5.030, 82.279%; tC2Q: 0.458, 7.497% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.088 | +
| Data Arrival Time | +8.845 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_l_21_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.845 | +1.602 | +tNET | +RR | +1 | +R11C5[1][B] | +main_tx_inst2/deserializer/sample_out_ch_2_l_21_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C5[1][B] | +main_tx_inst2/deserializer/sample_out_ch_2_l_21_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C5[1][B] | +main_tx_inst2/deserializer/sample_out_ch_2_l_21_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.223%; route: 5.030, 82.279%; tC2Q: 0.458, 7.497% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.088 | +
| Data Arrival Time | +8.845 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_1_l_17_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.845 | +1.602 | +tNET | +RR | +1 | +R11C5[1][A] | +main_tx_inst2/deserializer/sample_out_ch_1_l_17_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R11C5[1][A] | +main_tx_inst2/deserializer/sample_out_ch_1_l_17_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R11C5[1][A] | +main_tx_inst2/deserializer/sample_out_ch_1_l_17_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.223%; route: 5.030, 82.279%; tC2Q: 0.458, 7.497% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.073 | +
| Data Arrival Time | +8.473 | +
| Data Required Time | +6.400 | +
| From | +main_tx_inst/serializer/channel_cnt_1_s3 | +
| To | +main_tx_inst/serializer/ch_out_22_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R11C28[1][B] | +main_tx_inst/serializer/channel_cnt_1_s3/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +9 | +R11C28[1][B] | +main_tx_inst/serializer/channel_cnt_1_s3/Q | +
| 4.662 | +1.473 | +tNET | +FF | +1 | +R9C23[1][A] | +main_tx_inst/serializer/n285_s9/I1 | +
| 5.484 | +0.822 | +tINS | +FF | +22 | +R9C23[1][A] | +main_tx_inst/serializer/n285_s9/F | +
| 7.324 | +1.840 | +tNET | +FF | +1 | +R12C26[2][A] | +main_tx_inst/serializer/n382_s11/I2 | +
| 8.146 | +0.822 | +tINS | +FF | +1 | +R12C26[2][A] | +main_tx_inst/serializer/n382_s11/F | +
| 8.146 | +0.000 | +tNET | +FF | +1 | +R12C26[2][A] | +main_tx_inst/serializer/n382_s10/I0 | +
| 8.295 | +0.149 | +tINS | +FF | +1 | +R12C26[2][A] | +main_tx_inst/serializer/n382_s10/O | +
| 8.295 | +0.000 | +tNET | +FF | +1 | +R12C26[2][B] | +main_tx_inst/serializer/n382_s5/I1 | +
| 8.458 | +0.163 | +tINS | +FF | +1 | +R12C26[2][B] | +main_tx_inst/serializer/n382_s5/O | +
| 8.473 | +0.015 | +tNET | +FF | +1 | +R12C26[2][B] | +main_tx_inst/serializer/ch_out_22_s0/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R12C26[2][B] | +main_tx_inst/serializer/ch_out_22_s0/CLK | +
| 6.400 | +-0.400 | +tSu | ++ | 1 | +R12C26[2][B] | +main_tx_inst/serializer/ch_out_22_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +3 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 1.956, 34.065%; route: 3.328, 57.953%; tC2Q: 0.458, 7.982% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.073 | +
| Data Arrival Time | +8.473 | +
| Data Required Time | +6.400 | +
| From | +main_tx_inst2/serializer/channel_cnt_1_s3 | +
| To | +main_tx_inst2/serializer/ch_out_12_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R11C8[2][A] | +main_tx_inst2/serializer/channel_cnt_1_s3/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +9 | +R11C8[2][A] | +main_tx_inst2/serializer/channel_cnt_1_s3/Q | +
| 4.498 | +1.308 | +tNET | +FF | +1 | +R8C7[0][A] | +main_tx_inst2/serializer/n237_s2/I1 | +
| 5.124 | +0.626 | +tINS | +FF | +22 | +R8C7[0][A] | +main_tx_inst2/serializer/n237_s2/F | +
| 7.111 | +1.987 | +tNET | +FF | +1 | +R13C10[2][B] | +main_tx_inst2/serializer/n392_s12/I2 | +
| 8.137 | +1.026 | +tINS | +FR | +1 | +R13C10[2][B] | +main_tx_inst2/serializer/n392_s12/F | +
| 8.137 | +0.000 | +tNET | +RR | +1 | +R13C10[2][A] | +main_tx_inst2/serializer/n392_s10/I1 | +
| 8.287 | +0.150 | +tINS | +RR | +1 | +R13C10[2][A] | +main_tx_inst2/serializer/n392_s10/O | +
| 8.287 | +0.000 | +tNET | +RR | +1 | +R13C10[2][B] | +main_tx_inst2/serializer/n392_s5/I1 | +
| 8.464 | +0.177 | +tINS | +RR | +1 | +R13C10[2][B] | +main_tx_inst2/serializer/n392_s5/O | +
| 8.473 | +0.009 | +tNET | +RR | +1 | +R13C10[2][B] | +main_tx_inst2/serializer/ch_out_12_s0/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C10[2][B] | +main_tx_inst2/serializer/ch_out_12_s0/CLK | +
| 6.400 | +-0.400 | +tSu | ++ | 1 | +R13C10[2][B] | +main_tx_inst2/serializer/ch_out_12_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +3 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 1.979, 34.467%; route: 3.304, 57.550%; tC2Q: 0.458, 7.983% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.060 | +
| Data Arrival Time | +8.460 | +
| Data Required Time | +6.400 | +
| From | +main_tx_inst/serializer/channel_cnt_1_s3 | +
| To | +main_tx_inst/serializer/ch_out_10_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R11C28[1][B] | +main_tx_inst/serializer/channel_cnt_1_s3/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +9 | +R11C28[1][B] | +main_tx_inst/serializer/channel_cnt_1_s3/Q | +
| 4.662 | +1.473 | +tNET | +FF | +1 | +R9C23[1][A] | +main_tx_inst/serializer/n285_s9/I1 | +
| 5.484 | +0.822 | +tINS | +FF | +22 | +R9C23[1][A] | +main_tx_inst/serializer/n285_s9/F | +
| 7.499 | +2.015 | +tNET | +FF | +1 | +R12C28[2][A] | +main_tx_inst/serializer/n394_s11/I2 | +
| 8.124 | +0.625 | +tINS | +FR | +1 | +R12C28[2][A] | +main_tx_inst/serializer/n394_s11/F | +
| 8.124 | +0.000 | +tNET | +RR | +1 | +R12C28[2][A] | +main_tx_inst/serializer/n394_s10/I0 | +
| 8.274 | +0.150 | +tINS | +RR | +1 | +R12C28[2][A] | +main_tx_inst/serializer/n394_s10/O | +
| 8.274 | +0.000 | +tNET | +RR | +1 | +R12C28[2][B] | +main_tx_inst/serializer/n394_s5/I1 | +
| 8.451 | +0.177 | +tINS | +RR | +1 | +R12C28[2][B] | +main_tx_inst/serializer/n394_s5/O | +
| 8.460 | +0.009 | +tNET | +RR | +1 | +R12C28[2][B] | +main_tx_inst/serializer/ch_out_10_s0/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R12C28[2][B] | +main_tx_inst/serializer/ch_out_10_s0/CLK | +
| 6.400 | +-0.400 | +tSu | ++ | 1 | +R12C28[2][B] | +main_tx_inst/serializer/ch_out_10_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +3 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 1.774, 30.965%; route: 3.497, 61.035%; tC2Q: 0.458, 8.000% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.815 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_l_7_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.815 | +1.573 | +tNET | +RR | +1 | +R12C6[1][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_7_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R12C6[1][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_7_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R12C6[1][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_7_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.273%; route: 5.001, 82.194%; tC2Q: 0.458, 7.533% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.815 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_l_8_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.815 | +1.573 | +tNET | +RR | +1 | +R12C6[0][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_8_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R12C6[0][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_8_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R12C6[0][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_8_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.273%; route: 5.001, 82.194%; tC2Q: 0.458, 7.533% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.815 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.815 | +1.573 | +tNET | +RR | +1 | +R13C5[2][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C5[2][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C5[2][A] | +main_tx_inst2/deserializer/sample_out_ch_2_l_13_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.273%; route: 5.001, 82.194%; tC2Q: 0.458, 7.533% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.815 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_l_14_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.815 | +1.573 | +tNET | +RR | +1 | +R13C5[0][B] | +main_tx_inst2/deserializer/sample_out_ch_2_l_14_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C5[0][B] | +main_tx_inst2/deserializer/sample_out_ch_2_l_14_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C5[0][B] | +main_tx_inst2/deserializer/sample_out_ch_2_l_14_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.273%; route: 5.001, 82.194%; tC2Q: 0.458, 7.533% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.815 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_1_l_15_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.815 | +1.573 | +tNET | +RR | +1 | +R13C5[0][A] | +main_tx_inst2/deserializer/sample_out_ch_1_l_15_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C5[0][A] | +main_tx_inst2/deserializer/sample_out_ch_1_l_15_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C5[0][A] | +main_tx_inst2/deserializer/sample_out_ch_1_l_15_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.273%; route: 5.001, 82.194%; tC2Q: 0.458, 7.533% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.815 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_1_l_18_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.618 | +3.428 | +tNET | +FF | +1 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/I0 | +
| 7.243 | +0.625 | +tINS | +FR | +88 | +R16C9[0][B] | +main_tx_inst2/deserializer/n1844_s1/F | +
| 8.815 | +1.573 | +tNET | +RR | +1 | +R12C6[0][B] | +main_tx_inst2/deserializer/sample_out_ch_1_l_18_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R12C6[0][B] | +main_tx_inst2/deserializer/sample_out_ch_1_l_18_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R12C6[0][B] | +main_tx_inst2/deserializer/sample_out_ch_1_l_18_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.625, 10.273%; route: 5.001, 82.194%; tC2Q: 0.458, 7.533% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.058 | +
| Data Arrival Time | +8.459 | +
| Data Required Time | +6.400 | +
| From | +main_tx_inst2/serializer/channel_cnt_1_s3 | +
| To | +main_tx_inst2/serializer/ch_out_11_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R11C8[2][A] | +main_tx_inst2/serializer/channel_cnt_1_s3/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +9 | +R11C8[2][A] | +main_tx_inst2/serializer/channel_cnt_1_s3/Q | +
| 4.498 | +1.308 | +tNET | +FF | +1 | +R8C7[0][A] | +main_tx_inst2/serializer/n237_s2/I1 | +
| 5.124 | +0.626 | +tINS | +FF | +22 | +R8C7[0][A] | +main_tx_inst2/serializer/n237_s2/F | +
| 7.310 | +2.186 | +tNET | +FF | +1 | +R13C12[2][B] | +main_tx_inst2/serializer/n393_s12/I2 | +
| 8.132 | +0.822 | +tINS | +FF | +1 | +R13C12[2][B] | +main_tx_inst2/serializer/n393_s12/F | +
| 8.132 | +0.000 | +tNET | +FF | +1 | +R13C12[2][A] | +main_tx_inst2/serializer/n393_s10/I1 | +
| 8.281 | +0.149 | +tINS | +FF | +1 | +R13C12[2][A] | +main_tx_inst2/serializer/n393_s10/O | +
| 8.281 | +0.000 | +tNET | +FF | +1 | +R13C12[2][B] | +main_tx_inst2/serializer/n393_s5/I1 | +
| 8.444 | +0.163 | +tINS | +FF | +1 | +R13C12[2][B] | +main_tx_inst2/serializer/n393_s5/O | +
| 8.459 | +0.015 | +tNET | +FF | +1 | +R13C12[2][B] | +main_tx_inst2/serializer/ch_out_11_s0/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C12[2][B] | +main_tx_inst2/serializer/ch_out_11_s0/CLK | +
| 6.400 | +-0.400 | +tSu | ++ | 1 | +R13C12[2][B] | +main_tx_inst2/serializer/ch_out_11_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +3 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 1.760, 30.730%; route: 3.509, 61.267%; tC2Q: 0.458, 8.003% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.052 | +
| Data Arrival Time | +8.809 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_3_r_15_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.453 | +3.264 | +tNET | +FF | +1 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/I0 | +
| 7.255 | +0.802 | +tINS | +FR | +88 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/F | +
| 8.809 | +1.554 | +tNET | +RR | +1 | +R13C8[1][A] | +main_tx_inst2/deserializer/sample_out_ch_3_r_15_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C8[1][A] | +main_tx_inst2/deserializer/sample_out_ch_3_r_15_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C8[1][A] | +main_tx_inst2/deserializer/sample_out_ch_3_r_15_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.802, 13.195%; route: 4.818, 79.264%; tC2Q: 0.458, 7.541% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.052 | +
| Data Arrival Time | +8.809 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_r_5_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.453 | +3.264 | +tNET | +FF | +1 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/I0 | +
| 7.255 | +0.802 | +tINS | +FR | +88 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/F | +
| 8.809 | +1.554 | +tNET | +RR | +1 | +R13C8[1][B] | +main_tx_inst2/deserializer/sample_out_ch_2_r_5_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C8[1][B] | +main_tx_inst2/deserializer/sample_out_ch_2_r_5_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C8[1][B] | +main_tx_inst2/deserializer/sample_out_ch_2_r_5_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.802, 13.195%; route: 4.818, 79.264%; tC2Q: 0.458, 7.541% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.052 | +
| Data Arrival Time | +8.809 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_4_r_7_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.453 | +3.264 | +tNET | +FF | +1 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/I0 | +
| 7.255 | +0.802 | +tINS | +FR | +88 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/F | +
| 8.809 | +1.554 | +tNET | +RR | +1 | +R13C8[2][B] | +main_tx_inst2/deserializer/sample_out_ch_4_r_7_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C8[2][B] | +main_tx_inst2/deserializer/sample_out_ch_4_r_7_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C8[2][B] | +main_tx_inst2/deserializer/sample_out_ch_4_r_7_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.802, 13.196%; route: 4.817, 79.262%; tC2Q: 0.458, 7.542% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.052 | +
| Data Arrival Time | +8.809 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_2_r_7_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.453 | +3.264 | +tNET | +FF | +1 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/I0 | +
| 7.255 | +0.802 | +tINS | +FR | +88 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/F | +
| 8.809 | +1.554 | +tNET | +RR | +1 | +R13C8[0][B] | +main_tx_inst2/deserializer/sample_out_ch_2_r_7_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C8[0][B] | +main_tx_inst2/deserializer/sample_out_ch_2_r_7_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C8[0][B] | +main_tx_inst2/deserializer/sample_out_ch_2_r_7_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.802, 13.196%; route: 4.817, 79.262%; tC2Q: 0.458, 7.542% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.052 | +
| Data Arrival Time | +8.809 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_1_r_5_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.453 | +3.264 | +tNET | +FF | +1 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/I0 | +
| 7.255 | +0.802 | +tINS | +FR | +88 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/F | +
| 8.809 | +1.554 | +tNET | +RR | +1 | +R13C8[0][A] | +main_tx_inst2/deserializer/sample_out_ch_1_r_5_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C8[0][A] | +main_tx_inst2/deserializer/sample_out_ch_1_r_5_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C8[0][A] | +main_tx_inst2/deserializer/sample_out_ch_1_r_5_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Setup Relationship | +4.069 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
| Arrival Data Path Delay | +cell: 0.802, 13.196%; route: 4.817, 79.262%; tC2Q: 0.458, 7.542% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +
Path Summary:
+| Slack | +-2.052 | +
| Data Arrival Time | +8.809 | +
| Data Required Time | +6.757 | +
| From | +main_tx_inst/deserializer/bsync_pos_edge_s0 | +
| To | +main_tx_inst2/deserializer/sample_out_ch_1_r_7_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.731 | +0.244 | +tNET | +RR | +1 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/CLK | +
| 3.190 | +0.458 | +tC2Q | +RF | +20 | +R22C30[0][A] | +main_tx_inst/deserializer/bsync_pos_edge_s0/Q | +
| 6.453 | +3.264 | +tNET | +FF | +1 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/I0 | +
| 7.255 | +0.802 | +tINS | +FR | +88 | +R16C11[0][B] | +main_tx_inst2/deserializer/n1658_s1/F | +
| 8.809 | +1.554 | +tNET | +RR | +1 | +R13C8[2][A] | +main_tx_inst2/deserializer/sample_out_ch_1_r_7_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 4.069 | +4.069 | ++ | + | + | + | active clock edge time | +
| 4.069 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 6.556 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 6.800 | +0.244 | +tNET | +RR | +1 | +R13C8[2][A] | +main_tx_inst2/deserializer/sample_out_ch_1_r_7_s0/CLK | +
| 6.757 | +-0.043 | +tSu | ++ | 1 | +R13C8[2][A] | +main_tx_inst2/deserializer/sample_out_ch_1_r_7_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +||||||
| Setup Relationship | +4.069 | +||||||
| Logic Level | +2 | +||||||
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.244, 100.000% | +||||||
| Arrival Data Path Delay | +cell: 0.802, 13.196%; route: 4.817, 79.262%; tC2Q: 0.458, 7.542% | ||||||
| Required Clock Path Delay | @@ -6723,7 +6237,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }|||||||
| From | -main_tx_inst2/clocks/i2s_bclk_s2 | +main_tx_inst2/clocks/i2s_bclk_s1 | |||||
| To | @@ -6791,8 +6305,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2/CLK | +R24C16[0][A] | +main_tx_inst2/clocks/i2s_bclk_s1/CLK |
| 1.910 | @@ -6800,8 +6314,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 2 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2/Q | +R24C16[0][A] | +main_tx_inst2/clocks/i2s_bclk_s1/Q |
| 2.561 | @@ -6809,7 +6323,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R23C14[1][A] | +R24C14[2][A] | main_tx_inst2/deserializer/zbclk_s0/D |
| Slack | -0.379 | +0.408 | |||||||
| Data Arrival Time | -3.081 | +3.110 | |||||||
| Data Required Time | @@ -6923,7 +6437,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }|||||||||
| From | -main_tx_inst/clocks/i2s_lrclk_s2 | +main_tx_inst/clocks/i2s_lrclk_s1 | |||||||
| To | @@ -6991,8 +6505,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R24C28[2][A] | -main_tx_inst/clocks/i2s_lrclk_s2/CLK | +R24C28[1][A] | +main_tx_inst/clocks/i2s_lrclk_s1/CLK | ||
| 1.910 | @@ -7000,16 +6514,16 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 6 | -R24C28[2][A] | -main_tx_inst/clocks/i2s_lrclk_s2/Q | +R24C28[1][A] | +main_tx_inst/clocks/i2s_lrclk_s1/Q | ||
| 3.081 | -1.172 | +3.110 | +1.200 | tNET | RR | 1 | -R16C26[2][B] | +R16C24[0][B] | main_tx_inst/deserializer/zlrclk_s0/D |
| Slack | -0.389 | +0.427 | |||||||
| Data Arrival Time | -3.091 | +3.129 | |||||||
| Data Required Time | @@ -7123,7 +6637,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }|||||||||
| From | -main_tx_inst2/clocks/i2s_lrclk_s2 | +main_tx_inst2/clocks/i2s_lrclk_s1 | |||||||
| To | @@ -7191,8 +6705,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R18C16[1][B] | -main_tx_inst2/clocks/i2s_lrclk_s2/CLK | +R22C14[2][A] | +main_tx_inst2/clocks/i2s_lrclk_s1/CLK | ||
| 1.910 | @@ -7200,16 +6714,16 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 5 | -R18C16[1][B] | -main_tx_inst2/clocks/i2s_lrclk_s2/Q | +R22C14[2][A] | +main_tx_inst2/clocks/i2s_lrclk_s1/Q | ||
| 3.091 | -1.181 | +3.129 | +1.219 | tNET | RR | 1 | -R16C12[2][B] | +R17C10[2][B] | main_tx_inst2/deserializer/zlrclk_s0/D |
| Slack | -0.407 | +0.438 |
| Data Arrival Time | -3.109 | +3.140 |
| Data Required Time | @@ -7323,7 +6837,225 @@ table.detail_table th.label { min-width: 8%; width: 8%; }||
| From | -main_tx_inst/clocks/i2s_bclk_s2 | +main_tx_inst2/clocks/i2s_lrclk_s1 | +
| To | +main_tx_inst2/deserializer/new_data_s0 | +|
| Launch Clk | +i2s_in_sclk:[R] | +|
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | i2s_in_sclk | +
| 0.000 | +0.000 | +tCL | +RR | +1 | +IOB29[A] | +i2s_in_sclk_ibuf/I | +
| 1.392 | +1.392 | +tINS | +RR | +420 | +IOB29[A] | +i2s_in_sclk_ibuf/O | +
| 1.577 | +0.185 | +tNET | +RR | +1 | +R22C14[2][A] | +main_tx_inst2/clocks/i2s_lrclk_s1/CLK | +
| 1.910 | +0.333 | +tC2Q | +RR | +5 | +R22C14[2][A] | +main_tx_inst2/clocks/i2s_lrclk_s1/Q | +
| 2.414 | +0.504 | +tNET | +RR | +1 | +R24C14[0][B] | +main_tx_inst2/deserializer/n74_s0/I0 | +
| 3.140 | +0.726 | +tINS | +RR | +1 | +R24C14[0][B] | +main_tx_inst2/deserializer/n74_s0/F | +
| 3.140 | +0.000 | +tNET | +RR | +1 | +R24C14[0][B] | +main_tx_inst2/deserializer/new_data_s0/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.672 | +0.185 | +tNET | +RR | +1 | +R24C14[0][B] | +main_tx_inst2/deserializer/new_data_s0/CLK | +
| 2.702 | +0.030 | +tUnc | ++ | + | + | main_tx_inst2/deserializer/new_data_s0 | +
| 2.702 | +0.000 | +tHld | ++ | 1 | +R24C14[0][B] | +main_tx_inst2/deserializer/new_data_s0 | +
Path Statistics:
+| Clock Skew | +1.095 | +
| Hold Relationship | +0.000 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 1.392, 88.292%; route: 0.185, 11.708% | +
| Arrival Data Path Delay | +cell: 0.726, 46.449%; route: 0.504, 32.225%; tC2Q: 0.333, 21.326% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
Path Summary:
+| Slack | +0.449 | +||||||||
| Data Arrival Time | +3.150 | +||||||||
| Data Required Time | +2.702 | +||||||||
| From | +main_tx_inst/clocks/i2s_bclk_s1 | ||||||||
| To | @@ -7391,8 +7123,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R24C22[0][A] | -main_tx_inst/clocks/i2s_bclk_s2/CLK | +R23C22[0][A] | +main_tx_inst/clocks/i2s_bclk_s1/CLK | ||
| 1.910 | @@ -7400,16 +7132,16 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 3 | -R24C22[0][A] | -main_tx_inst/clocks/i2s_bclk_s2/Q | +R23C22[0][A] | +main_tx_inst/clocks/i2s_bclk_s1/Q | ||
| 3.109 | -1.199 | +3.150 | +1.241 | tNET | RR | 1 | -R22C32[0][A] | +R22C29[0][B] | main_tx_inst/deserializer/zbclk_s0/D |
Path Summary:
-| Slack | -0.425 | -
| Data Arrival Time | -3.127 | -
| Data Required Time | -2.702 | -
| From | -main_tx_inst/clocks/aes_lrclk_s2 | -
| To | -main_tx_inst/serializer/zaes_lrck_s0 | -
| Launch Clk | -i2s_in_sclk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | i2s_in_sclk | -
| 0.000 | -0.000 | -tCL | -RR | -1 | -IOB29[A] | -i2s_in_sclk_ibuf/I | -
| 1.392 | -1.392 | -tINS | -RR | -420 | -IOB29[A] | -i2s_in_sclk_ibuf/O | -
| 1.577 | -0.185 | -tNET | -RR | -1 | -R23C26[1][A] | -main_tx_inst/clocks/aes_lrclk_s2/CLK | -
| 1.910 | -0.333 | -tC2Q | -RR | -2 | -R23C26[1][A] | -main_tx_inst/clocks/aes_lrclk_s2/Q | -
| 3.127 | -1.217 | -tNET | -RR | -1 | -R9C26[2][A] | -main_tx_inst/serializer/zaes_lrck_s0/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.672 | -0.185 | -tNET | -RR | -1 | -R9C26[2][A] | -main_tx_inst/serializer/zaes_lrck_s0/CLK | -
| 2.702 | -0.030 | -tUnc | -- | - | - | main_tx_inst/serializer/zaes_lrck_s0 | -
| 2.702 | -0.000 | -tHld | -- | 1 | -R9C26[2][A] | -main_tx_inst/serializer/zaes_lrck_s0 | -
Path Statistics:
-| Clock Skew | -1.095 | -||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Hold Relationship | -0.000 | -||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Logic Level | -1 | -||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Arrival Clock Path Delay | -cell: 1.392, 88.292%; route: 0.185, 11.708% | -||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Arrival Data Path Delay | -cell: 0.000, 0.000%; route: 1.217, 78.496%; tC2Q: 0.333, 21.504% | +cell: 0.000, 0.000%; route: 1.241, 78.821%; tC2Q: 0.333, 21.179% | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Required Clock Path Delay | @@ -7711,11 +7243,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
| Slack | -0.506 | +0.515 | |||||||
| Data Arrival Time | -3.208 | +3.217 | |||||||
| Data Required Time | @@ -7723,7 +7255,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }|||||||||
| From | -main_tx_inst/clocks/i2s_lrclk_s2 | +main_tx_inst/clocks/i2s_lrclk_s1 | |||||||
| To | @@ -7791,8 +7323,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R24C28[2][A] | -main_tx_inst/clocks/i2s_lrclk_s2/CLK | +R24C28[1][A] | +main_tx_inst/clocks/i2s_lrclk_s1/CLK | ||
| 1.910 | @@ -7800,34 +7332,34 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 6 | -R24C28[2][A] | -main_tx_inst/clocks/i2s_lrclk_s2/Q | +R24C28[1][A] | +main_tx_inst/clocks/i2s_lrclk_s1/Q | ||
| 2.484 | -0.574 | +2.491 | +0.581 | tNET | RR | 1 | -R22C29[1][B] | +R21C28[2][B] | main_tx_inst/deserializer/n74_s0/I0 |
| 3.208 | -0.724 | +3.217 | +0.726 | tINS | RR | 1 | -R22C29[1][B] | +R21C28[2][B] | main_tx_inst/deserializer/n74_s0/F |
| 3.208 | +3.217 | 0.000 | tNET | RR | 1 | -R22C29[1][B] | +R21C28[2][B] | main_tx_inst/deserializer/new_data_s0/D |
Data Required Path:
@@ -8056,7 +7588,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Statistics:
@@ -8115,19 +7647,19 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Data Required Path:
@@ -8239,26 +7771,26 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Statistics:
@@ -8277,7 +7809,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }| Slack | -0.561 | +0.587 |
| Data Arrival Time | -3.187 | -|
| Data Required Time | -2.626 | -|
| From | -main_rx_1_inst/receiver/aes3_clk_s0 | -|
| To | -main_rx_1_inst/receiver/decoder_shift_7_s0 | -|
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | -|
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | -
| 2.429 | -2.429 | -tCL | -RR | -531 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUTD | -
| 2.614 | -0.185 | -tNET | -RR | -1 | -R5C37[1][B] | -main_rx_1_inst/receiver/aes3_clk_s0/CLK | -
| 2.947 | -0.333 | -tC2Q | -RR | -18 | -R5C37[1][B] | -main_rx_1_inst/receiver/aes3_clk_s0/Q | -
| 3.187 | -0.240 | -tNET | -RR | -1 | -R5C37[2][A] | -main_rx_1_inst/receiver/decoder_shift_7_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | -
| 2.429 | -2.429 | -tCL | -RR | -531 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUTD | -
| 2.614 | -0.185 | -tNET | -RR | -1 | -R5C37[2][A] | -main_rx_1_inst/receiver/decoder_shift_7_s0/CLK | -
| 2.626 | -0.012 | -tHld | -- | 1 | -R5C37[2][A] | -main_rx_1_inst/receiver/decoder_shift_7_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Hold Relationship | -0.000 | -
| Logic Level | -1 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
| Arrival Data Path Delay | -cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
Path Summary:
-| Slack | -0.565 | -||||||||
| Data Arrival Time | -3.191 | +3.213 | |||||||
| Data Required Time | @@ -8536,7 +7886,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }2.429 | tCL | RR | -531 | +693 | PLL_R | pll_main_clock/rpll_inst/CLKOUTD | tNET | RR | 1 | -R21C34[1][A] | +R15C34[0][B] | main_rx_1_inst/clocks/zzaes_lrclk_s0/CLK |
| tC2Q | RR | 3 | -R21C34[1][A] | +R15C34[0][B] | main_rx_1_inst/clocks/zzaes_lrclk_s0/Q | ||||
| 3.191 | -0.244 | +3.213 | +0.266 | tNET | RR | 1 | -R21C34[0][A] | +R15C33[0][A] | main_rx_1_inst/clocks/aes_lrclk_pos_edge_s0/RESET |
Path Summary:
| Slack | -0.567 | +0.587 |
| Data Arrival Time | -3.251 | +1.858 |
| Data Required Time | -2.684 | +1.271 |
| From | -main_tx_inst/deserializer/bsync_pos_edge_s0 | +main_rx_1_inst/clocks/zzbsync_s0 |
| To | -main_tx_inst/deserializer/new_data_s0 | +main_rx_1_inst/clocks/bsync_pos_edge_s0 |
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +main_rx_1_inst/aes3_bclk:[R] |
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +main_rx_1_inst/aes3_bclk:[R] |
Data Arrival Path:
@@ -8711,225 +8061,43 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.672 | -0.185 | -tNET | -RR | -1 | -R22C29[1][B] | -main_tx_inst/deserializer/new_data_s0/CLK | -
| 2.684 | -0.012 | -tHld | -- | 1 | -R22C29[1][B] | -main_tx_inst/deserializer/new_data_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Hold Relationship | -0.000 | -
| Logic Level | -1 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
| Arrival Data Path Delay | -cell: 0.000, 0.000%; route: 0.246, 42.446%; tC2Q: 0.333, 57.554% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
Path Summary:
-| Slack | -0.590 | -
| Data Arrival Time | -3.274 | -
| Data Required Time | -2.684 | -
| From | -main_tx_inst/deserializer/zzbsync_s0 | -
| To | -main_tx_inst/deserializer/bsync_pos_edge_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -||||
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -||||
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -||||
| 2.672 | -0.185 | -tNET | -RR | -1 | -R22C31[0][B] | -main_tx_inst/deserializer/zzbsync_s0/CLK | -||||
| 3.005 | +1.592 | 0.333 | tC2Q | RR | 2 | -R22C31[0][B] | -main_tx_inst/deserializer/zzbsync_s0/Q | +R22C33[0][B] | +main_rx_1_inst/clocks/zzbsync_s0/Q | |
| 3.274 | -0.269 | +1.858 | +0.266 | tNET | RR | 1 | -R22C29[0][B] | -main_tx_inst/deserializer/bsync_pos_edge_s0/RESET | +R22C34[0][A] | +main_rx_1_inst/clocks/bsync_pos_edge_s0/RESET |
Data Required Path:
@@ -8959,34 +8127,34 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Statistics:
@@ -9005,18 +8173,18 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Summary:
| To | -main_tx_inst2/serializer/ch_out_1_s0 | +main_tx_inst2/serializer/ch_out_5_s0 | |||||
| Launch Clk | @@ -9110,8 +8278,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R6C11[1][A] | -main_tx_inst2/serializer/ch_out_1_s0/CE | +R6C8[2][B] | +main_tx_inst2/serializer/ch_out_5_s0/CE |
Data Required Path:
@@ -9158,8 +8326,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Statistics:
@@ -9198,6 +8366,370 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Summary:
+| Slack | +0.595 | +
| Data Arrival Time | +3.280 | +
| Data Required Time | +2.684 | +
| From | +main_tx_inst2/serializer/aes_lrck_edge_s0 | +
| To | +main_tx_inst2/serializer/ch_out_6_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.672 | +0.185 | +tNET | +RR | +1 | +R6C10[0][B] | +main_tx_inst2/serializer/aes_lrck_edge_s0/CLK | +
| 3.005 | +0.333 | +tC2Q | +RR | +28 | +R6C10[0][B] | +main_tx_inst2/serializer/aes_lrck_edge_s0/Q | +
| 3.280 | +0.274 | +tNET | +RR | +1 | +R6C9[2][B] | +main_tx_inst2/serializer/ch_out_6_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.672 | +0.185 | +tNET | +RR | +1 | +R6C9[2][B] | +main_tx_inst2/serializer/ch_out_6_s0/CLK | +
| 2.684 | +0.012 | +tHld | ++ | 1 | +R6C9[2][B] | +main_tx_inst2/serializer/ch_out_6_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Hold Relationship | +0.000 | +
| Logic Level | +1 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
| Arrival Data Path Delay | +cell: 0.000, 0.000%; route: 0.274, 45.149%; tC2Q: 0.333, 54.851% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
Path Summary:
+| Slack | +0.596 | +
| Data Arrival Time | +3.281 | +
| Data Required Time | +2.684 | +
| From | +main_tx_inst/serializer/aes_lrck_edge_s0 | +
| To | +main_tx_inst/serializer/ch_out_0_s0 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.672 | +0.185 | +tNET | +RR | +1 | +R9C18[0][B] | +main_tx_inst/serializer/aes_lrck_edge_s0/CLK | +
| 3.005 | +0.333 | +tC2Q | +RR | +28 | +R9C18[0][B] | +main_tx_inst/serializer/aes_lrck_edge_s0/Q | +
| 3.281 | +0.276 | +tNET | +RR | +1 | +R9C20[2][A] | +main_tx_inst/serializer/ch_out_0_s0/CE | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | +
| 2.487 | +2.487 | +tCL | +RR | +1164 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUT | +
| 2.672 | +0.185 | +tNET | +RR | +1 | +R9C20[2][A] | +main_tx_inst/serializer/ch_out_0_s0/CLK | +
| 2.684 | +0.012 | +tHld | ++ | 1 | +R9C20[2][A] | +main_tx_inst/serializer/ch_out_0_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Hold Relationship | +0.000 | +
| Logic Level | +1 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
| Arrival Data Path Delay | +cell: 0.000, 0.000%; route: 0.276, 45.255%; tC2Q: 0.333, 54.745% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
Path Summary:
| Slack | -0.603 | -
| Data Arrival Time | -3.287 | -
| Data Required Time | -2.684 | -
| From | -main_tx_inst2/serializer/aes_lrck_edge_s0 | -
| To | -main_tx_inst2/serializer/ch_out_7_s0 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.672 | -0.185 | -tNET | -RR | -1 | -R6C10[0][B] | -main_tx_inst2/serializer/aes_lrck_edge_s0/CLK | -
| 3.005 | -0.333 | -tC2Q | -RR | -28 | -R6C10[0][B] | -main_tx_inst2/serializer/aes_lrck_edge_s0/Q | -
| 3.287 | -0.282 | -tNET | -RR | -1 | -R6C8[2][B] | -main_tx_inst2/serializer/ch_out_7_s0/CE | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.672 | -0.185 | -tNET | -RR | -1 | -R6C8[2][B] | -main_tx_inst2/serializer/ch_out_7_s0/CLK | -
| 2.684 | -0.012 | -tHld | -- | 1 | -R6C8[2][B] | -main_tx_inst2/serializer/ch_out_7_s0 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Hold Relationship | -0.000 | -
| Logic Level | -1 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
| Arrival Data Path Delay | -cell: 0.000, 0.000%; route: 0.282, 45.818%; tC2Q: 0.333, 54.182% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
Path Summary:
-| Slack | -0.708 | -
| Data Arrival Time | -3.380 | -
| Data Required Time | -2.672 | -
| From | -main_tx_inst/deserializer/bit_cnt_4_s4 | -
| To | -main_tx_inst/deserializer/bit_cnt_4_s4 | -
| Launch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
| Latch Clk | -pll_main_clock/rpll_inst/CLKOUT.default_gen_clk:[R] | -
Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.672 | -0.185 | -tNET | -RR | -1 | -R22C32[1][A] | -main_tx_inst/deserializer/bit_cnt_4_s4/CLK | -
| 3.005 | -0.333 | -tC2Q | -RR | -4 | -R22C32[1][A] | -main_tx_inst/deserializer/bit_cnt_4_s4/Q | -
| 3.008 | -0.002 | -tNET | -RR | -1 | -R22C32[1][A] | -main_tx_inst/deserializer/n44_s3/I0 | -
| 3.380 | -0.372 | -tINS | -RF | -1 | -R22C32[1][A] | -main_tx_inst/deserializer/n44_s3/F | -
| 3.380 | -0.000 | -tNET | -FF | -1 | -R22C32[1][A] | -main_tx_inst/deserializer/bit_cnt_4_s4/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | pll_main_clock/rpll_inst/CLKOUT.default_gen_clk | -
| 2.487 | -2.487 | -tCL | -RR | -1164 | -PLL_R | -pll_main_clock/rpll_inst/CLKOUT | -
| 2.672 | -0.185 | -tNET | -RR | -1 | -R22C32[1][A] | -main_tx_inst/deserializer/bit_cnt_4_s4/CLK | -
| 2.672 | -0.000 | -tHld | -- | 1 | -R22C32[1][A] | -main_tx_inst/deserializer/bit_cnt_4_s4 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Hold Relationship | -0.000 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
| Arrival Data Path Delay | -cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% | -
| Required Clock Path Delay | -cell: 0.000, 0.000%; route: 0.185, 100.000% | -
Path Summary:
-| Slack | 0.708 | ||||
| tNET | RR | 1 | -R16C26[1][A] | +R16C25[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/CLK |
| tC2Q | RR | 2 | -R16C26[1][A] | +R16C25[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/Q |
| tNET | RR | 1 | -R16C26[1][A] | +R16C25[0][A] | main_tx_inst/deserializer/n30_s2/I0 |
| tINS | RF | 1 | -R16C26[1][A] | +R16C25[0][A] | main_tx_inst/deserializer/n30_s2/F |
| tNET | FF | 1 | -R16C26[1][A] | +R16C25[0][A] | main_tx_inst/deserializer/lrck_neg_edge_s4/D |
Path Summary:
+| Slack | +0.708 | +
| Data Arrival Time | +3.322 | +
| Data Required Time | +2.614 | +
| From | +main_rx_1_inst/transmitter/bclk_neg_edge_s4 | +
| To | +main_rx_1_inst/transmitter/bclk_neg_edge_s4 | +
| Launch Clk | +pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | +
| Latch Clk | +pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | +
| 2.429 | +2.429 | +tCL | +RR | +693 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUTD | +
| 2.614 | +0.185 | +tNET | +RR | +1 | +R12C41[0][A] | +main_rx_1_inst/transmitter/bclk_neg_edge_s4/CLK | +
| 2.947 | +0.333 | +tC2Q | +RR | +5 | +R12C41[0][A] | +main_rx_1_inst/transmitter/bclk_neg_edge_s4/Q | +
| 2.950 | +0.002 | +tNET | +RR | +1 | +R12C41[0][A] | +main_rx_1_inst/transmitter/n8_s2/I0 | +
| 3.322 | +0.372 | +tINS | +RF | +1 | +R12C41[0][A] | +main_rx_1_inst/transmitter/n8_s2/F | +
| 3.322 | +0.000 | +tNET | +FF | +1 | +R12C41[0][A] | +main_rx_1_inst/transmitter/bclk_neg_edge_s4/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk | +
| 2.429 | +2.429 | +tCL | +RR | +693 | +PLL_R | +pll_main_clock/rpll_inst/CLKOUTD | +
| 2.614 | +0.185 | +tNET | +RR | +1 | +R12C41[0][A] | +main_rx_1_inst/transmitter/bclk_neg_edge_s4/CLK | +
| 2.614 | +0.000 | +tHld | ++ | 1 | +R12C41[0][A] | +main_rx_1_inst/transmitter/bclk_neg_edge_s4 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Hold Relationship | +0.000 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
| Arrival Data Path Delay | +cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% | +
| Required Clock Path Delay | +cell: 0.000, 0.000%; route: 0.185, 100.000% | +
Path Summary:
| tNET | RR | 1 | -R11C17[0][A] | +R11C16[0][A] | main_tx_inst2/transmitter/data_biphase_s1/CLK |
| tC2Q | RR | 2 | -R11C17[0][A] | +R11C16[0][A] | main_tx_inst2/transmitter/data_biphase_s1/Q |
| tNET | RR | 1 | -R11C17[0][A] | +R11C16[0][A] | main_tx_inst2/transmitter/n2535_s2/I0 |
| tINS | RF | 1 | -R11C17[0][A] | +R11C16[0][A] | main_tx_inst2/transmitter/n2535_s2/F |
| tNET | FF | 1 | -R11C17[0][A] | +R11C16[0][A] | main_tx_inst2/transmitter/data_biphase_s1/D |
Path Summary:
+| Slack | +0.708 | +
| Data Arrival Time | +2.284 | +
| Data Required Time | +1.577 | +
| From | +main_tx_inst2/clocks/aes_lrclk_s1 | +
| To | +main_tx_inst2/clocks/aes_lrclk_s1 | +
| Launch Clk | +i2s_in_sclk:[R] | +
| Latch Clk | +i2s_in_sclk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | i2s_in_sclk | +
| 0.000 | +0.000 | +tCL | +RR | +1 | +IOB29[A] | +i2s_in_sclk_ibuf/I | +
| 1.392 | +1.392 | +tINS | +RR | +420 | +IOB29[A] | +i2s_in_sclk_ibuf/O | +
| 1.577 | +0.185 | +tNET | +RR | +1 | +R14C16[0][A] | +main_tx_inst2/clocks/aes_lrclk_s1/CLK | +
| 1.910 | +0.333 | +tC2Q | +RR | +2 | +R14C16[0][A] | +main_tx_inst2/clocks/aes_lrclk_s1/Q | +
| 1.912 | +0.002 | +tNET | +RR | +1 | +R14C16[0][A] | +main_tx_inst2/clocks/n264_s2/I0 | +
| 2.284 | +0.372 | +tINS | +RF | +1 | +R14C16[0][A] | +main_tx_inst2/clocks/n264_s2/F | +
| 2.284 | +0.000 | +tNET | +FF | +1 | +R14C16[0][A] | +main_tx_inst2/clocks/aes_lrclk_s1/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | i2s_in_sclk | +
| 0.000 | +0.000 | +tCL | +RR | +1 | +IOB29[A] | +i2s_in_sclk_ibuf/I | +
| 1.392 | +1.392 | +tINS | +RR | +420 | +IOB29[A] | +i2s_in_sclk_ibuf/O | +
| 1.577 | +0.185 | +tNET | +RR | +1 | +R14C16[0][A] | +main_tx_inst2/clocks/aes_lrclk_s1/CLK | +
| 1.577 | +0.000 | +tHld | ++ | 1 | +R14C16[0][A] | +main_tx_inst2/clocks/aes_lrclk_s1 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Hold Relationship | +0.000 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 1.392, 88.292%; route: 0.185, 11.708% | +
| Arrival Data Path Delay | +cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% | +
| Required Clock Path Delay | +cell: 1.392, 88.292%; route: 0.185, 11.708% | +
Path Summary:
| From | -main_tx_inst2/clocks/aes_lrclk_s2 | +main_tx_inst2/clocks/i2s_bclk_s1 | |||||
| To | -main_tx_inst2/clocks/aes_lrclk_s2 | +main_tx_inst2/clocks/i2s_bclk_s1 | |||||
| Launch Clk | @@ -10265,8 +9833,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R15C16[0][A] | -main_tx_inst2/clocks/aes_lrclk_s2/CLK | +R24C16[0][A] | +main_tx_inst2/clocks/i2s_bclk_s1/CLK |
| 1.910 | @@ -10274,8 +9842,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 2 | -R15C16[0][A] | -main_tx_inst2/clocks/aes_lrclk_s2/Q | +R24C16[0][A] | +main_tx_inst2/clocks/i2s_bclk_s1/Q |
| 1.912 | @@ -10283,8 +9851,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R15C16[0][A] | -main_tx_inst2/clocks/n264_s3/I0 | +R24C16[0][A] | +main_tx_inst2/clocks/n43_s2/I0 |
| 2.284 | @@ -10292,8 +9860,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tINS | RF | 1 | -R15C16[0][A] | -main_tx_inst2/clocks/n264_s3/F | +R24C16[0][A] | +main_tx_inst2/clocks/n43_s2/F |
| 2.284 | @@ -10301,8 +9869,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | FF | 1 | -R15C16[0][A] | -main_tx_inst2/clocks/aes_lrclk_s2/D | +R24C16[0][A] | +main_tx_inst2/clocks/i2s_bclk_s1/D |
Data Required Path:
@@ -10358,8 +9926,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Statistics:
@@ -10415,224 +9983,6 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Data Arrival Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | i2s_in_sclk | -
| 0.000 | -0.000 | -tCL | -RR | -1 | -IOB29[A] | -i2s_in_sclk_ibuf/I | -
| 1.392 | -1.392 | -tINS | -RR | -420 | -IOB29[A] | -i2s_in_sclk_ibuf/O | -
| 1.577 | -0.185 | -tNET | -RR | -1 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2/CLK | -
| 1.910 | -0.333 | -tC2Q | -RR | -2 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2/Q | -
| 1.912 | -0.002 | -tNET | -RR | -1 | -R23C16[0][A] | -main_tx_inst2/clocks/n43_s3/I0 | -
| 2.284 | -0.372 | -tINS | -RF | -1 | -R23C16[0][A] | -main_tx_inst2/clocks/n43_s3/F | -
| 2.284 | -0.000 | -tNET | -FF | -1 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2/D | -
Data Required Path:
-| AT | -DELAY | -TYPE | -RF | -FANOUT | -LOC | -NODE | -
|---|---|---|---|---|---|---|
| 0.000 | -0.000 | -- | - | - | - | active clock edge time | -
| 0.000 | -0.000 | -- | - | - | - | i2s_in_sclk | -
| 0.000 | -0.000 | -tCL | -RR | -1 | -IOB29[A] | -i2s_in_sclk_ibuf/I | -
| 1.392 | -1.392 | -tINS | -RR | -420 | -IOB29[A] | -i2s_in_sclk_ibuf/O | -
| 1.577 | -0.185 | -tNET | -RR | -1 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2/CLK | -
| 1.577 | -0.000 | -tHld | -- | 1 | -R23C16[0][A] | -main_tx_inst2/clocks/i2s_bclk_s2 | -
Path Statistics:
-| Clock Skew | -0.000 | -
| Hold Relationship | -0.000 | -
| Logic Level | -2 | -
| Arrival Clock Path Delay | -cell: 1.392, 88.292%; route: 0.185, 11.708% | -
| Arrival Data Path Delay | -cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% | -
| Required Clock Path Delay | -cell: 1.392, 88.292%; route: 0.185, 11.708% | -
Path Summary:
-| Slack | -0.708 | -||||
| Data Arrival Time | -2.284 | -||||
| Data Required Time | -1.577 | -||||
| From | main_tx_inst2/clocks/count_aes_lrclk_0_s0 | ||||
| tNET | RR | 1 | -R15C17[0][A] | +R15C15[1][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/CLK |
| tC2Q | RR | 3 | -R15C17[0][A] | +R15C15[1][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/Q |
| tNET | RR | 1 | -R15C17[0][A] | +R15C15[1][A] | main_tx_inst2/clocks/n255_s2/I0 |
| tINS | RF | 1 | -R15C17[0][A] | +R15C15[1][A] | main_tx_inst2/clocks/n255_s2/F |
| tNET | FF | 1 | -R15C17[0][A] | +R15C15[1][A] | main_tx_inst2/clocks/count_aes_lrclk_0_s0/D |
Path Summary:
| tNET | RR | 1 | -R18C17[0][A] | +R20C16[1][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/CLK |
| tC2Q | RR | 3 | -R18C17[0][A] | +R20C16[1][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/Q |
| tNET | RR | 1 | -R18C17[0][A] | +R20C16[1][A] | main_tx_inst2/clocks/n143_s2/I0 |
| tINS | RF | 1 | -R18C17[0][A] | +R20C16[1][A] | main_tx_inst2/clocks/n143_s2/F |
| tNET | FF | 1 | -R18C17[0][A] | +R20C16[1][A] | main_tx_inst2/clocks/count_i2s_lrclk_0_s0/D |
Path Summary:
| tNET | RR | 1 | -R23C17[0][A] | +R24C16[1][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/CLK |
| tC2Q | RR | 3 | -R23C17[0][A] | +R24C16[1][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/Q |
| tNET | RR | 1 | -R23C17[0][A] | +R24C16[1][A] | main_tx_inst2/clocks/n38_s2/I0 |
| tINS | RF | 1 | -R23C17[0][A] | +R24C16[1][A] | main_tx_inst2/clocks/n38_s2/F |
| tNET | FF | 1 | -R23C17[0][A] | +R24C16[1][A] | main_tx_inst2/clocks/count_i2s_bclk_0_s0/D |
Path Summary:
| From | -main_tx_inst/clocks/aes_lrclk_s2 | +main_tx_inst/clocks/aes_lrclk_s1 | |||||
| To | -main_tx_inst/clocks/aes_lrclk_s2 | +main_tx_inst/clocks/aes_lrclk_s1 | |||||
| Launch Clk | @@ -11355,8 +10705,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R23C26[1][A] | -main_tx_inst/clocks/aes_lrclk_s2/CLK | +R23C25[1][A] | +main_tx_inst/clocks/aes_lrclk_s1/CLK |
| 1.910 | @@ -11364,8 +10714,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tC2Q | RR | 2 | -R23C26[1][A] | -main_tx_inst/clocks/aes_lrclk_s2/Q | +R23C25[1][A] | +main_tx_inst/clocks/aes_lrclk_s1/Q |
| 1.912 | @@ -11373,8 +10723,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | RR | 1 | -R23C26[1][A] | -main_tx_inst/clocks/n264_s3/I0 | +R23C25[1][A] | +main_tx_inst/clocks/n264_s2/I0 |
| 2.284 | @@ -11382,8 +10732,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tINS | RF | 1 | -R23C26[1][A] | -main_tx_inst/clocks/n264_s3/F | +R23C25[1][A] | +main_tx_inst/clocks/n264_s2/F |
| 2.284 | @@ -11391,8 +10741,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }tNET | FF | 1 | -R23C26[1][A] | -main_tx_inst/clocks/aes_lrclk_s2/D | +R23C25[1][A] | +main_tx_inst/clocks/aes_lrclk_s1/D |
Data Required Path:
@@ -11448,8 +10798,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Statistics:
@@ -11488,7 +10838,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }Path Summary:
| tNET | RR | 1 | -R23C26[0][A] | +R23C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/CLK |
| tC2Q | RR | 3 | -R23C26[0][A] | +R23C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/Q |
| tNET | RR | 1 | -R23C26[0][A] | +R23C25[0][A] | main_tx_inst/clocks/n255_s2/I0 |
| tINS | RF | 1 | -R23C26[0][A] | +R23C25[0][A] | main_tx_inst/clocks/n255_s2/F |
| tNET | FF | 1 | -R23C26[0][A] | +R23C25[0][A] | main_tx_inst/clocks/count_aes_lrclk_0_s0/D |
Path Summary:
+| Slack | +0.708 | +
| Data Arrival Time | +2.284 | +
| Data Required Time | +1.577 | +
| From | +main_tx_inst/clocks/count_i2s_bclk_0_s0 | +
| To | +main_tx_inst/clocks/count_i2s_bclk_0_s0 | +
| Launch Clk | +i2s_in_sclk:[R] | +
| Latch Clk | +i2s_in_sclk:[R] | +
Data Arrival Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | i2s_in_sclk | +
| 0.000 | +0.000 | +tCL | +RR | +1 | +IOB29[A] | +i2s_in_sclk_ibuf/I | +
| 1.392 | +1.392 | +tINS | +RR | +420 | +IOB29[A] | +i2s_in_sclk_ibuf/O | +
| 1.577 | +0.185 | +tNET | +RR | +1 | +R23C22[1][A] | +main_tx_inst/clocks/count_i2s_bclk_0_s0/CLK | +
| 1.910 | +0.333 | +tC2Q | +RR | +3 | +R23C22[1][A] | +main_tx_inst/clocks/count_i2s_bclk_0_s0/Q | +
| 1.912 | +0.002 | +tNET | +RR | +1 | +R23C22[1][A] | +main_tx_inst/clocks/n38_s2/I0 | +
| 2.284 | +0.372 | +tINS | +RF | +1 | +R23C22[1][A] | +main_tx_inst/clocks/n38_s2/F | +
| 2.284 | +0.000 | +tNET | +FF | +1 | +R23C22[1][A] | +main_tx_inst/clocks/count_i2s_bclk_0_s0/D | +
Data Required Path:
+| AT | +DELAY | +TYPE | +RF | +FANOUT | +LOC | +NODE | +
|---|---|---|---|---|---|---|
| 0.000 | +0.000 | ++ | + | + | + | active clock edge time | +
| 0.000 | +0.000 | ++ | + | + | + | i2s_in_sclk | +
| 0.000 | +0.000 | +tCL | +RR | +1 | +IOB29[A] | +i2s_in_sclk_ibuf/I | +
| 1.392 | +1.392 | +tINS | +RR | +420 | +IOB29[A] | +i2s_in_sclk_ibuf/O | +
| 1.577 | +0.185 | +tNET | +RR | +1 | +R23C22[1][A] | +main_tx_inst/clocks/count_i2s_bclk_0_s0/CLK | +
| 1.577 | +0.000 | +tHld | ++ | 1 | +R23C22[1][A] | +main_tx_inst/clocks/count_i2s_bclk_0_s0 | +
Path Statistics:
+| Clock Skew | +0.000 | +
| Hold Relationship | +0.000 | +
| Logic Level | +2 | +
| Arrival Clock Path Delay | +cell: 1.392, 88.292%; route: 0.185, 11.708% | +
| Arrival Data Path Delay | +cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% | +
| Required Clock Path Delay | +cell: 1.392, 88.292%; route: 0.185, 11.708% | +