From a741df208c2625e54d15a544bbb47fe7c55e585d Mon Sep 17 00:00:00 2001 From: TheStaticTurtle Date: Sat, 4 Oct 2025 16:57:45 +0200 Subject: [PATCH] Rewrote ultranet_rx_demux to sync&use the channel index the sample data --- .../impl/gwsynthesis/test_fpga_project.log | 25 +- .../impl/gwsynthesis/test_fpga_project.prj | 2 +- .../impl/gwsynthesis/test_fpga_project.vg | 18056 ++++++++-------- .../test_fpga_project_syn.rpt.html | 48 +- .../test_fpga_project_syn_resource.html | 14 +- .../gwsynthesis/test_fpga_project_syn_rsc.xml | 12 +- .../impl/pnr/test_fpga_project.bin | Bin 258574 -> 258574 bytes .../impl/pnr/test_fpga_project.binx | Bin 259095 -> 259095 bytes .../impl/pnr/test_fpga_project.db | Bin 68220 -> 70920 bytes .../impl/pnr/test_fpga_project.fs | 1268 +- .../impl/pnr/test_fpga_project.log | 2 +- .../impl/pnr/test_fpga_project.pin.html | 2 +- .../impl/pnr/test_fpga_project.power.html | 50 +- .../impl/pnr/test_fpga_project.rpt.html | 58 +- .../impl/pnr/test_fpga_project.rpt.txt | 38 +- .../impl/pnr/test_fpga_project.timing_paths | 868 +- .../pnr/test_fpga_project_tr_content.html | 13922 ++++++------ .../impl/temp/rtl_parser.result | 8 +- .../impl/temp/rtl_parser_arg.json | 10 +- src/hdl/test_fpga_project/src/main_rx.v | 5 +- .../src/ultranet_rx_demux.vhd | 116 +- .../src/ultranet_rx_deserializer.vhd | 14 +- .../test_fpga_project.gprj.user | 2 +- 23 files changed, 17127 insertions(+), 17393 deletions(-) diff --git a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log index 88569c8..1cbcbce 100644 --- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log +++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log @@ -25,19 +25,19 @@ Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\te Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd' Analyzing entity 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19) Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":37) -Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd' -Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":12) -Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":36) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd' Analyzing entity 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18) -Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":45) +Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":44) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd' Analyzing entity 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6) Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":26) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd' Analyzing entity 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6) Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":18) -WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":136) +Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd' +Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6) +Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":30) +WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":135) Compiling module 'top'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":2) Compiling module 'gowin_rpll_245'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10) Compiling module 'main_rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":2) @@ -47,15 +47,16 @@ Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\H Switching to VHDL mode to elaborate design unit 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":50) Processing 'ultranet_rx_clocks(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19) Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":50) -Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":70) +Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":68) Processing 'ultranet_rx_deserializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18) -Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":70) -Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":98) -Processing 'ultranet_rx_demux(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":12) -Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":98) -Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":121) +Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":68) +Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":95) +Processing 'ultranet_rx_demux(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6) +'others' clause is never selected("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":81) +Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":95) +Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":118) Processing 'i2s_quad_transmitter(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd":11) -Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":121) +Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":118) Compiling module 'main_tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":2) Switching to VHDL mode to elaborate design unit 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":38) Processing 'ultranet_tx_clocks(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6) diff --git a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj index b6e2901..15aa432 100644 --- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj +++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj @@ -15,10 +15,10 @@ - +