From ab7ec343d4ed6adc66281e4e619d91fd06f4c95b Mon Sep 17 00:00:00 2001 From: TheStaticTurtle Date: Sat, 4 Oct 2025 23:30:40 +0200 Subject: [PATCH] Rewrote aes3tx and updaed serialiser --- .../impl/gwsynthesis/test_fpga_project.log | 27 +- .../impl/gwsynthesis/test_fpga_project.prj | 3 +- .../impl/gwsynthesis/test_fpga_project.vg | 18156 ++++++++-------- .../test_fpga_project_syn.rpt.html | 833 +- .../test_fpga_project_syn_resource.html | 34 +- .../gwsynthesis/test_fpga_project_syn_rsc.xml | 26 +- .../impl/pnr/test_fpga_project.bin | Bin 258574 -> 258574 bytes .../impl/pnr/test_fpga_project.binx | Bin 259095 -> 259095 bytes .../impl/pnr/test_fpga_project.db | Bin 70920 -> 69260 bytes .../impl/pnr/test_fpga_project.fs | 1318 +- .../impl/pnr/test_fpga_project.log | 2 +- .../impl/pnr/test_fpga_project.pin.html | 2 +- .../impl/pnr/test_fpga_project.power.html | 121 +- .../impl/pnr/test_fpga_project.rpt.html | 63 +- .../impl/pnr/test_fpga_project.rpt.txt | 43 +- .../impl/pnr/test_fpga_project.timing_paths | 1210 +- .../impl/pnr/test_fpga_project_tr_cata.html | 2 +- .../pnr/test_fpga_project_tr_content.html | 11545 +++++----- .../impl/temp/rtl_parser.result | 28 +- .../impl/temp/rtl_parser_arg.json | 7 +- src/hdl/test_fpga_project/src/aes3tx.vhd | 10 +- src/hdl/test_fpga_project/src/aes3tx2.vhd | 163 + src/hdl/test_fpga_project/src/main.v | 5 +- src/hdl/test_fpga_project/src/main_tx.v | 26 +- .../src/ultranet_serializer.vhd | 44 +- .../test_fpga_project/test_fpga_project.gprj | 1 + .../test_fpga_project.gprj.user | 2 +- 27 files changed, 17581 insertions(+), 16090 deletions(-) create mode 100644 src/hdl/test_fpga_project/src/aes3tx2.vhd diff --git a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log index 1cbcbce..a4f2416 100644 --- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log +++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log @@ -9,7 +9,7 @@ Analyzing entity 'aes3rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_pr Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd":39) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd' Analyzing entity 'aes3tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":11) -Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":32) +Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":34) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd' Analyzing entity 'i2s_deser'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd":17) Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd":35) @@ -25,19 +25,22 @@ Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\te Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd' Analyzing entity 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19) Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":37) +Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd' +Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6) +Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":30) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd' Analyzing entity 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18) Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":44) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd' Analyzing entity 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6) -Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":26) +Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":28) Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd' Analyzing entity 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6) Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":18) -Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd' -Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6) -Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":30) -WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":135) +Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd' +Analyzing entity 'aes3tx2'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd":5) +Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd":28) +WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":136) Compiling module 'top'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":2) Compiling module 'gowin_rpll_245'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10) Compiling module 'main_rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":2) @@ -64,13 +67,14 @@ Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\H Switching to VHDL mode to elaborate design unit 'i2s_quad_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":75) Processing 'i2s_quad_deserializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd":7) Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":75) -Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":99) +Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":103) Processing 'ultranet_serializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6) -Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":99) -Switching to VHDL mode to elaborate design unit 'aes3tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":114) -Processing 'aes3tx(behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":11) -Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":114) +Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":103) +Switching to VHDL mode to elaborate design unit 'aes3tx2'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":118) +Processing 'aes3tx2(behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd":5) +Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":118) NOTE (EX0101) : Current top module is "top" +WARN (EX0211) : The output port "bsync" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":17) WARN (EX0211) : The output port "debug_4" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":20) WARN (EX0211) : The output port "debug_2" of module "top" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":44) [5%] Running netlist conversion ... @@ -81,7 +85,6 @@ WARN (CV0016) : Input ultranet_rx_2 is unused("C:\Projects\In Progress\HyperNet WARN (CV0016) : Input key_2 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":40) WARN (CV0016) : Input key_3 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":41) Running device independent optimization ... -WARN (DI0019) : Merging user defined instance "main_tx_inst2/transmitter/bit_counter[5:0]" to instance "main_tx_inst/transmitter/bit_counter[5:0]", because they are equivalent. If you want to keep the instance, please apply property constraint syn_preserve = 1 on it("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":50) [10%] Optimizing Phase 0 completed [15%] Optimizing Phase 1 completed [25%] Optimizing Phase 2 completed diff --git a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj index 15aa432..a97851b 100644 --- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj +++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj @@ -15,10 +15,11 @@ + - +