module main_rx (
    input  reset_n,        // Active-low reset

    input  dir_sclk,       // Input DIR system clock (24.576 MHz)
    input  dir_bclk,       // Input DIR bit clock (12.288 MHz)
    input  dir_lrclk,      // Input DIR word clock (192 kHz)
    input  dir_data,       // Input DIR audio data
    input  dir_bframe,     // Input DIR B-frame indicator

    output i2s_out_sclk,   // Output I2S system clock (12.288 MHz)
    output i2s_out_bclk,   // Output I2S bit clock (3.072 MHz)
    output i2s_out_lrclk,  // Output I2S word clock (48 kHz)
    output i2s_out_data_1, // Output I2S channels 1+2
    output i2s_out_data_2, // Output I2S channels 3+4
    output i2s_out_data_3, // Output I2S channels 5+6
    output i2s_out_data_4  // Output I2S channels 7+8
);

// Pulse indicating new set of samples ready
wire audio_sample_load;

// Audio sample data wires (24-bit each)
wire [23:0] audio_sample_1;
wire [23:0] audio_sample_2;
wire [23:0] audio_sample_3;
wire [23:0] audio_sample_4;
wire [23:0] audio_sample_5;
wire [23:0] audio_sample_6;
wire [23:0] audio_sample_7;
wire [23:0] audio_sample_8;


// Hypernet receiver / DIR interface: extracts 8 channels of 24-bit samples
hypernet_rx rx(
	.reset_n(reset_n),

	.bclk(dir_bclk),     // Input DIR bit clock (12.288 MHz)
	.lrclk(dir_lrclk),   // Input DIR word clock (48 kHz)
	.sdata(dir_data),    // Input DIR audio data
	//.bsync(dir_bframe),  // Input DIR Frame sync signal

	.ch1_out(audio_sample_1),  // Output audio channel 1
	.ch2_out(audio_sample_2),  // Output audio channel 2
	.ch3_out(audio_sample_3),  // Output audio channel 3
	.ch4_out(audio_sample_4),  // Output audio channel 4
	.ch5_out(audio_sample_5),  // Output audio channel 5
	.ch6_out(audio_sample_6),  // Output audio channel 6
	.ch7_out(audio_sample_7),  // Output audio channel 7
	.ch8_out(audio_sample_8),  // Output audio channel 8

	.is_end_of_frame(audio_sample_load) // Frame finished, asserted at the end of channel 8
);

// Clock divider: generates I2S system clock (12.288 MHz) from AES3 clock (49.152 MHz)
Gowin_CLKDIV4 sclk_div(
    .hclkin(dir_sclk),     // Input recovered clock from the DIR (49.152 MHz)
    .resetn(reset_n),

    .clkout(i2s_out_sclk)  // Output I2S system clock (12.288 MHz)
);
// I2S clock generator: derives bit and word clocks from I2S system clock and aligns them with the AES3 b-frame signal
hypernet_synced_i2s_clocks clocks(
	.sclk(i2s_out_sclk),   // Input I2S system clock (12.288 MHz)
    .reset_n(reset_n),

	.sync(dir_bframe),     // Input AES3 B-Frame signal

	.bclk(i2s_out_bclk),   // Output I2S bit clock (3.072 MHz)
	.lrclk(i2s_out_lrclk)  // Output I2S word clock (48 kHz)
);

// I2S transmitter: converts 8 audio channels into 4 stereo I2S outputs
i2s_quad_transmitter transmitter(
	.clk(dir_sclk),         // Master clock (49.152 MHz) TODO: Rewrite this module to use the I2S system clock
	.reset_n(reset_n),
    
	.bclk(i2s_out_bclk),    // I2S bit clock (3.072 MHz)
	.lrclk(i2s_out_lrclk),  // I2S word clock (48 kHz)
    
    .sample_load(audio_sample_load), // Load new samples when frame ends

    // Map 8 input channels into 4 stereo pairs (L/R)
	.sample_ch_1_l({ audio_sample_1, 8'b00000000}), // Ch1 left (32-bit padded)
	.sample_ch_1_r({ audio_sample_2, 8'b00000000}), // Ch2 right 
	.sample_ch_2_l({ audio_sample_3, 8'b00000000}), // Ch3 left 
	.sample_ch_2_r({ audio_sample_4, 8'b00000000}), // Ch4 right 
	.sample_ch_3_l({ audio_sample_5, 8'b00000000}), // Ch5 left
	.sample_ch_3_r({ audio_sample_6, 8'b00000000}), // Ch6 right 
	.sample_ch_4_l({ audio_sample_7, 8'b00000000}), // Ch7 left
	.sample_ch_4_r({ audio_sample_8, 8'b00000000}), // Ch8 right

	// I2S serial outputs for 4 stereo links
	.sdout_1(i2s_out_data_1),
	.sdout_2(i2s_out_data_2),
	.sdout_3(i2s_out_data_3),
	.sdout_4(i2s_out_data_4)
);

endmodule