Moved code used for the v1 prototype

2025-08-20 22:34:26 +02:00 · 2025-08-20 22:34:26 +02:00 · 6a8e9843bb
commit 6a8e9843bb
parent 26af26ed24
44 changed files with 0 additions and 0 deletions
--- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log
+++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log
--- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj
+++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj
--- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.vg
+++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.vg
--- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn.rpt.html
+++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn.rpt.html
--- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_resource.html
+++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_resource.html
--- a/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_rsc.xml
+++ b/src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_rsc.xml
--- a/src/hdl/test_fpga_project/impl/pnr/cmd.do
+++ b/src/hdl/test_fpga_project/impl/pnr/cmd.do
--- a/src/hdl/test_fpga_project/impl/pnr/device.cfg
+++ b/src/hdl/test_fpga_project/impl/pnr/device.cfg
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.bin
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.bin
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.binx
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.binx
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.db
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.db
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.fs
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.fs
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.log
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.log
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.pin.html
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.pin.html
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.power.html
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.power.html
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.txt
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.txt
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.timing_paths
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.timing_paths
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.tr.html
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project.tr.html
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project_tr_cata.html
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project_tr_cata.html
--- a/src/hdl/test_fpga_project/impl/pnr/test_fpga_project_tr_content.html
+++ b/src/hdl/test_fpga_project/impl/pnr/test_fpga_project_tr_content.html
--- a/src/hdl/test_fpga_project/impl/temp/rtl_parser.result
+++ b/src/hdl/test_fpga_project/impl/temp/rtl_parser.result
--- a/src/hdl/test_fpga_project/impl/temp/rtl_parser_arg.json
+++ b/src/hdl/test_fpga_project/impl/temp/rtl_parser_arg.json
--- a/src/hdl/test_fpga_project/impl/temp/style.css
+++ b/src/hdl/test_fpga_project/impl/temp/style.css
--- a/src/hdl/test_fpga_project/impl/test_fpga_project_process_config.json
+++ b/src/hdl/test_fpga_project/impl/test_fpga_project_process_config.json
--- a/src/hdl/test_fpga_project/src/aes3rx.vhd
+++ b/src/hdl/test_fpga_project/src/aes3rx.vhd
--- a/src/hdl/test_fpga_project/src/aes3tx.vhd
+++ b/src/hdl/test_fpga_project/src/aes3tx.vhd
--- a/src/hdl/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v
+++ b/src/hdl/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v
--- a/src/hdl/test_fpga_project/src/i2s_deser.vhd
+++ b/src/hdl/test_fpga_project/src/i2s_deser.vhd
--- a/src/hdl/test_fpga_project/src/i2s_quad_deserializer.vhd
+++ b/src/hdl/test_fpga_project/src/i2s_quad_deserializer.vhd
--- a/src/hdl/test_fpga_project/src/i2s_quad_transmitter.vhd
+++ b/src/hdl/test_fpga_project/src/i2s_quad_transmitter.vhd
--- a/src/hdl/test_fpga_project/src/main.cst
+++ b/src/hdl/test_fpga_project/src/main.cst
--- a/src/hdl/test_fpga_project/src/main.v
+++ b/src/hdl/test_fpga_project/src/main.v
--- a/src/hdl/test_fpga_project/src/main_rx.v
+++ b/src/hdl/test_fpga_project/src/main_rx.v
--- a/src/hdl/test_fpga_project/src/main_tx.v
+++ b/src/hdl/test_fpga_project/src/main_tx.v
--- a/src/hdl/test_fpga_project/src/spdif_transmitter.vhd
+++ b/src/hdl/test_fpga_project/src/spdif_transmitter.vhd
--- a/src/hdl/test_fpga_project/src/test_fpga_project.sdc
+++ b/src/hdl/test_fpga_project/src/test_fpga_project.sdc
--- a/src/hdl/test_fpga_project/src/ultranet_rx_clocks.vhd
+++ b/src/hdl/test_fpga_project/src/ultranet_rx_clocks.vhd
--- a/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd
+++ b/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd
--- a/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd
+++ b/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd
--- a/src/hdl/test_fpga_project/src/ultranet_serializer.vhd
+++ b/src/hdl/test_fpga_project/src/ultranet_serializer.vhd
--- a/src/hdl/test_fpga_project/src/ultranet_tx_clocks.vhd
+++ b/src/hdl/test_fpga_project/src/ultranet_tx_clocks.vhd
--- a/src/hdl/test_fpga_project/test_fpga_project.gprj
+++ b/src/hdl/test_fpga_project/test_fpga_project.gprj
--- a/src/hdl/test_fpga_project/test_fpga_project.gprj.user
+++ b/src/hdl/test_fpga_project/test_fpga_project.gprj.user