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Fixed (-ish) transmiter implementation

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This commit is contained in:
Samuel TUGLER 2025-10-04 00:14:06 +02:00
parent ecc0110525
commit c641559228
Signed by: samuel.tugler
GPG Key ID: C97F759321C4C29C
25 changed files with 16926 additions and 15066 deletions
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src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.log
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@ -1,86 +1,86 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v'
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v'
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v'
Analyzing Verilog file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v'
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd'
Analyzing entity 'aes3rx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd":14)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd":39)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd'
Analyzing entity 'i2s_deser'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd":17)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd":35)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd'
Analyzing entity 'i2s_quad_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd":33)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd'
Analyzing entity 'i2s_quad_transmitter'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd":42)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd'
Analyzing entity 'spdif_transmitter'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd":12)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd":21)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd'
Analyzing entity 'ultranet_rx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd":37)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd'
Analyzing entity 'ultranet_serializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd":6)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd":26)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd'
Analyzing entity 'ultranet_tx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd":18)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd'
Analyzing entity 'ultranet_rx_demux'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd":12)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd":36)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd'
Analyzing entity 'ultranet_rx_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
Analyzing architecture 'rtl'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd":45)
Analyzing VHDL file 'C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd'
Analyzing entity 'aes3tx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":11)
Analyzing architecture 'behavioral'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":32)
WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":135)
Compiling module 'top'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":2)
Compiling module 'gowin_rpll_245'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10)
Compiling module 'main_rx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":2)
Switching to VHDL mode to elaborate design unit 'aes3rx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":35)
Processing 'aes3rx(Behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd":14)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":35)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":50)
Processing 'ultranet_rx_clocks(Behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":50)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":70)
Processing 'ultranet_rx_deserializer(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":70)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":98)
Processing 'ultranet_rx_demux(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd":12)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":98)
Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":121)
Processing 'i2s_quad_transmitter(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v":121)
Compiling module 'main_tx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":2)
Switching to VHDL mode to elaborate design unit 'ultranet_tx_clocks'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":38)
Processing 'ultranet_tx_clocks(Behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":38)
Switching to VHDL mode to elaborate design unit 'i2s_quad_deserializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":75)
Processing 'i2s_quad_deserializer(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":75)
Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":99)
Processing 'ultranet_serializer(rtl)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd":6)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":99)
Switching to VHDL mode to elaborate design unit 'aes3tx'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":114)
Processing 'aes3tx(behavioral)'("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":11)
Returning to Verilog mode to proceed with elaboration("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":114)
Analyzing Verilog file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v'
Analyzing Verilog file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v'
Analyzing Verilog file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v'
Analyzing Verilog file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v'
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd'
Analyzing entity 'aes3rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd":14)
Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd":39)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd'
Analyzing entity 'aes3tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":11)
Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":32)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd'
Analyzing entity 'i2s_deser'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd":17)
Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd":35)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd'
Analyzing entity 'i2s_quad_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd":33)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd'
Analyzing entity 'i2s_quad_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd":42)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd'
Analyzing entity 'spdif_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd":12)
Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd":21)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd'
Analyzing entity 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":37)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd'
Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":12)
Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":36)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd'
Analyzing entity 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":45)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd'
Analyzing entity 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6)
Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":26)
Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd'
Analyzing entity 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":18)
WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":136)
Compiling module 'top'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":2)
Compiling module 'gowin_rpll_245'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10)
Compiling module 'main_rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":2)
Switching to VHDL mode to elaborate design unit 'aes3rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":35)
Processing 'aes3rx(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd":14)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":35)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":50)
Processing 'ultranet_rx_clocks(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":50)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":70)
Processing 'ultranet_rx_deserializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":70)
Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":98)
Processing 'ultranet_rx_demux(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":12)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":98)
Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":121)
Processing 'i2s_quad_transmitter(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":121)
Compiling module 'main_tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":2)
Switching to VHDL mode to elaborate design unit 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":38)
Processing 'ultranet_tx_clocks(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":38)
Switching to VHDL mode to elaborate design unit 'i2s_quad_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":75)
Processing 'i2s_quad_deserializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":75)
Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":99)
Processing 'ultranet_serializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":99)
Switching to VHDL mode to elaborate design unit 'aes3tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":114)
Processing 'aes3tx(behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":11)
Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":114)
NOTE (EX0101) : Current top module is "top"
WARN (EX0211) : The output port "debug_4" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":20)
WARN (EX0211) : The output port "debug_2" of module "top" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":44)
WARN (EX0211) : The output port "debug_4" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":20)
WARN (EX0211) : The output port "debug_2" of module "top" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":44)
[5%] Running netlist conversion ...
WARN (CV0016) : Input sys_clk is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":3)
WARN (CV0016) : Input aes3_rx is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":6)
WARN (CV0016) : Input sfp_rx is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":7)
WARN (CV0016) : Input ultranet_rx_2 is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":9)
WARN (CV0016) : Input key_2 is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":40)
WARN (CV0016) : Input key_3 is unused("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v":41)
WARN (CV0016) : Input sys_clk is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":3)
WARN (CV0016) : Input aes3_rx is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":6)
WARN (CV0016) : Input sfp_rx is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":7)
WARN (CV0016) : Input ultranet_rx_2 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":9)
WARN (CV0016) : Input key_2 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":40)
WARN (CV0016) : Input key_3 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":41)
Running device independent optimization ...
WARN (DI0019) : Merging user defined instance "main_tx_inst2/transmitter/bit_counter[5:0]" to instance "main_tx_inst/transmitter/bit_counter[5:0]", because they are equivalent. If you want to keep the instance, please apply property constraint syn_preserve = 1 on it("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd":50)
WARN (DI0019) : Merging user defined instance "main_tx_inst2/transmitter/bit_counter[5:0]" to instance "main_tx_inst/transmitter/bit_counter[5:0]", because they are equivalent. If you want to keep the instance, please apply property constraint syn_preserve = 1 on it("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":50)
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
@ -95,11 +95,8 @@ Running technical mapping ...
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ultranet_tx_clocks" instantiated to "clocks" is swept in optimizing("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":30)
WARN (NL0002) : The module "i2s_quad_deserializer" instantiated to "deserializer" is swept in optimizing("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":53)
WARN (NL0002) : The module "ultranet_serializer" instantiated to "serializer" is swept in optimizing("C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v":82)
[95%] Generate netlist file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg" completed
[95%] Generate netlist file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg" completed
WARN (CK3000) : Can't calculate clocks' relationship between: "main_rx_1_inst/receiver/aes3_bclk" and "pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk"
WARN (CK3000) : Can't calculate clocks' relationship between: "pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk" and "main_rx_1_inst/receiver/aes3_bclk"
[100%] Generate report file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project_syn.rpt.html" completed
[100%] Generate report file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project_syn.rpt.html" completed
GowinSynthesis finish

32
src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.prj
View File

@ -4,27 +4,27 @@
<Version>beta</Version>
<Device id="GW1NR-9C" package="QFN88P" speed="6" partNumber="GW1NR-LV9QN88PC6/I5"/>
<FileList>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v" type="verilog"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v" type="verilog"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v" type="verilog"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v" type="verilog"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd" type="vhdl"/>
<File path="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v" type="verilog"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v" type="verilog"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v" type="verilog"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v" type="verilog"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd" type="vhdl"/>
<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd" type="vhdl"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="50.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg"/>
<Option type="output_file" value="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="top_module" value="top"/>

15362
src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project.vg
View File

File diff suppressed because it is too large Load Diff

270
src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn.rpt.html
View File

@ -55,21 +55,21 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.v<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_rx.v<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main_tx.v<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3rx.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_deser.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_deserializer.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\i2s_quad_transmitter.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\spdif_transmitter.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_clocks.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_serializer.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_tx_clocks.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_demux.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\ultranet_rx_deserializer.vhd<br>
C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\aes3tx.vhd<br>
<td>C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\main.v<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd<br>
C:\Projects\In&nbspProgress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd<br>
</td>
</tr>
<tr>
@ -94,7 +94,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Mar 18 23:31:35 2025
<td>Sat Oct 4 00:10:56 2025
</td>
</tr>
<tr>
@ -110,11 +110,11 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.459s, Peak memory usage = 337.070MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.412s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.368s, Peak memory usage = 337.070MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 337.070MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 337.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 337.070MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 337.070MB<br/></td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 330.844MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.239s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 330.844MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 330.844MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 330.844MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 330.844MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 330.844MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 337.070MB</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 330.844MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
@ -146,63 +146,63 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>1527</td>
<td>2151</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>63</td>
<td>81</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>1039</td>
<td>1570</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>2</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>32</td>
<td>35</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>165</td>
<td>269</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>226</td>
<td>193</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>498</td>
<td>676</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>48</td>
<td>66</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>283</td>
<td>391</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>167</td>
<td>219</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>150</td>
<td>243</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>150</td>
<td>243</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>27</td>
<td>31</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>27</td>
<td>31</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
@ -222,13 +222,13 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">Logic</td>
<td>675(525 LUT, 150 ALU) / 8640</td>
<td>8%</td>
<td>950(707 LUT, 243 ALU) / 8640</td>
<td>11%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1527 / 6693</td>
<td>23%</td>
<td>2151 / 6693</td>
<td>33%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
@ -237,8 +237,8 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>1527 / 6693</td>
<td>23%</td>
<td>2151 / 6693</td>
<td>33%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
@ -348,7 +348,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1</td>
<td>i2s_in_sclk</td>
<td>24.576(MHz)</td>
<td>85.724(MHz)</td>
<td>82.841(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
@ -395,11 +395,11 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">From</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>main_tx_inst/serializer/ch_out_0_s0</td>
<td>main_tx_inst2/serializer/ch_out_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
@ -433,7 +433,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -442,15 +442,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/CLK</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/CLK</td>
</tr>
<tr>
<td>2.340</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/Q</td>
<td>9</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/Q</td>
</tr>
<tr>
<td>3.300</td>
@ -458,15 +458,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n237_s2/I1</td>
<td>main_tx_inst2/serializer/n237_s2/I1</td>
</tr>
<tr>
<td>4.399</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>main_tx_inst/serializer/n237_s2/F</td>
<td>22</td>
<td>main_tx_inst2/serializer/n237_s2/F</td>
</tr>
<tr>
<td>5.359</td>
@ -474,7 +474,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n404_s12/I2</td>
<td>main_tx_inst2/serializer/n402_s12/I2</td>
</tr>
<tr>
<td>6.181</td>
@ -482,7 +482,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n404_s12/F</td>
<td>main_tx_inst2/serializer/n402_s12/F</td>
</tr>
<tr>
<td>7.141</td>
@ -490,7 +490,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n404_s10/I1</td>
<td>main_tx_inst2/serializer/n402_s10/I1</td>
</tr>
<tr>
<td>7.290</td>
@ -498,7 +498,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n404_s10/O</td>
<td>main_tx_inst2/serializer/n402_s10/O</td>
</tr>
<tr>
<td>8.250</td>
@ -506,7 +506,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n404_s5/I1</td>
<td>main_tx_inst2/serializer/n402_s5/I1</td>
</tr>
<tr>
<td>8.413</td>
@ -514,7 +514,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n404_s5/O</td>
<td>main_tx_inst2/serializer/n402_s5/O</td>
</tr>
<tr>
<td>9.373</td>
@ -522,7 +522,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_0_s0/D</td>
<td>main_tx_inst2/serializer/ch_out_2_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
@ -548,7 +548,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -557,7 +557,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_0_s0/CLK</td>
<td>main_tx_inst2/serializer/ch_out_2_s0/CLK</td>
</tr>
<tr>
<td>5.551</td>
@ -565,7 +565,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tSu</td>
<td> </td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_0_s0</td>
<td>main_tx_inst2/serializer/ch_out_2_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
@ -607,11 +607,11 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">From</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>main_tx_inst/serializer/ch_out_1_s0</td>
<td>main_tx_inst2/serializer/ch_out_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
@ -645,7 +645,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -654,15 +654,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/CLK</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/CLK</td>
</tr>
<tr>
<td>2.340</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/Q</td>
<td>9</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/Q</td>
</tr>
<tr>
<td>3.300</td>
@ -670,15 +670,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n237_s2/I1</td>
<td>main_tx_inst2/serializer/n237_s2/I1</td>
</tr>
<tr>
<td>4.399</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>main_tx_inst/serializer/n237_s2/F</td>
<td>22</td>
<td>main_tx_inst2/serializer/n237_s2/F</td>
</tr>
<tr>
<td>5.359</td>
@ -686,7 +686,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n403_s12/I2</td>
<td>main_tx_inst2/serializer/n401_s12/I2</td>
</tr>
<tr>
<td>6.181</td>
@ -694,7 +694,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n403_s12/F</td>
<td>main_tx_inst2/serializer/n401_s12/F</td>
</tr>
<tr>
<td>7.141</td>
@ -702,7 +702,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n403_s10/I1</td>
<td>main_tx_inst2/serializer/n401_s10/I1</td>
</tr>
<tr>
<td>7.290</td>
@ -710,7 +710,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n403_s10/O</td>
<td>main_tx_inst2/serializer/n401_s10/O</td>
</tr>
<tr>
<td>8.250</td>
@ -718,7 +718,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n403_s5/I1</td>
<td>main_tx_inst2/serializer/n401_s5/I1</td>
</tr>
<tr>
<td>8.413</td>
@ -726,7 +726,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n403_s5/O</td>
<td>main_tx_inst2/serializer/n401_s5/O</td>
</tr>
<tr>
<td>9.373</td>
@ -734,7 +734,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_1_s0/D</td>
<td>main_tx_inst2/serializer/ch_out_3_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
@ -760,7 +760,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -769,7 +769,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_1_s0/CLK</td>
<td>main_tx_inst2/serializer/ch_out_3_s0/CLK</td>
</tr>
<tr>
<td>5.551</td>
@ -777,7 +777,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tSu</td>
<td> </td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_1_s0</td>
<td>main_tx_inst2/serializer/ch_out_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
@ -819,11 +819,11 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">From</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>main_tx_inst/serializer/ch_out_2_s0</td>
<td>main_tx_inst2/serializer/ch_out_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
@ -857,7 +857,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -866,15 +866,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/CLK</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/CLK</td>
</tr>
<tr>
<td>2.340</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/Q</td>
<td>9</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/Q</td>
</tr>
<tr>
<td>3.300</td>
@ -882,15 +882,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n237_s2/I1</td>
<td>main_tx_inst2/serializer/n237_s2/I1</td>
</tr>
<tr>
<td>4.399</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>main_tx_inst/serializer/n237_s2/F</td>
<td>22</td>
<td>main_tx_inst2/serializer/n237_s2/F</td>
</tr>
<tr>
<td>5.359</td>
@ -898,7 +898,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n402_s12/I2</td>
<td>main_tx_inst2/serializer/n400_s12/I2</td>
</tr>
<tr>
<td>6.181</td>
@ -906,7 +906,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n402_s12/F</td>
<td>main_tx_inst2/serializer/n400_s12/F</td>
</tr>
<tr>
<td>7.141</td>
@ -914,7 +914,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n402_s10/I1</td>
<td>main_tx_inst2/serializer/n400_s10/I1</td>
</tr>
<tr>
<td>7.290</td>
@ -922,7 +922,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n402_s10/O</td>
<td>main_tx_inst2/serializer/n400_s10/O</td>
</tr>
<tr>
<td>8.250</td>
@ -930,7 +930,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n402_s5/I1</td>
<td>main_tx_inst2/serializer/n400_s5/I1</td>
</tr>
<tr>
<td>8.413</td>
@ -938,7 +938,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n402_s5/O</td>
<td>main_tx_inst2/serializer/n400_s5/O</td>
</tr>
<tr>
<td>9.373</td>
@ -946,7 +946,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_2_s0/D</td>
<td>main_tx_inst2/serializer/ch_out_4_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
@ -972,7 +972,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -981,7 +981,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_2_s0/CLK</td>
<td>main_tx_inst2/serializer/ch_out_4_s0/CLK</td>
</tr>
<tr>
<td>5.551</td>
@ -989,7 +989,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tSu</td>
<td> </td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_2_s0</td>
<td>main_tx_inst2/serializer/ch_out_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
@ -1031,11 +1031,11 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">From</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>main_tx_inst/serializer/ch_out_3_s0</td>
<td>main_tx_inst2/serializer/ch_out_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
@ -1069,7 +1069,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -1078,15 +1078,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/CLK</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/CLK</td>
</tr>
<tr>
<td>2.340</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/Q</td>
<td>9</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/Q</td>
</tr>
<tr>
<td>3.300</td>
@ -1094,15 +1094,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n237_s2/I1</td>
<td>main_tx_inst2/serializer/n237_s2/I1</td>
</tr>
<tr>
<td>4.399</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>main_tx_inst/serializer/n237_s2/F</td>
<td>22</td>
<td>main_tx_inst2/serializer/n237_s2/F</td>
</tr>
<tr>
<td>5.359</td>
@ -1110,7 +1110,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n401_s12/I2</td>
<td>main_tx_inst2/serializer/n399_s12/I2</td>
</tr>
<tr>
<td>6.181</td>
@ -1118,7 +1118,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n401_s12/F</td>
<td>main_tx_inst2/serializer/n399_s12/F</td>
</tr>
<tr>
<td>7.141</td>
@ -1126,7 +1126,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n401_s10/I1</td>
<td>main_tx_inst2/serializer/n399_s10/I1</td>
</tr>
<tr>
<td>7.290</td>
@ -1134,7 +1134,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n401_s10/O</td>
<td>main_tx_inst2/serializer/n399_s10/O</td>
</tr>
<tr>
<td>8.250</td>
@ -1142,7 +1142,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n401_s5/I1</td>
<td>main_tx_inst2/serializer/n399_s5/I1</td>
</tr>
<tr>
<td>8.413</td>
@ -1150,7 +1150,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n401_s5/O</td>
<td>main_tx_inst2/serializer/n399_s5/O</td>
</tr>
<tr>
<td>9.373</td>
@ -1158,7 +1158,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_3_s0/D</td>
<td>main_tx_inst2/serializer/ch_out_5_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
@ -1184,7 +1184,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -1193,7 +1193,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_3_s0/CLK</td>
<td>main_tx_inst2/serializer/ch_out_5_s0/CLK</td>
</tr>
<tr>
<td>5.551</td>
@ -1201,7 +1201,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tSu</td>
<td> </td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_3_s0</td>
<td>main_tx_inst2/serializer/ch_out_5_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
@ -1243,11 +1243,11 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
</tr>
<tr>
<td class="label">From</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>main_tx_inst/serializer/ch_out_4_s0</td>
<td>main_tx_inst2/serializer/ch_out_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
@ -1281,7 +1281,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -1290,15 +1290,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/CLK</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/CLK</td>
</tr>
<tr>
<td>2.340</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>main_tx_inst/serializer/channel_cnt_1_s3/Q</td>
<td>9</td>
<td>main_tx_inst2/serializer/channel_cnt_1_s3/Q</td>
</tr>
<tr>
<td>3.300</td>
@ -1306,15 +1306,15 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n237_s2/I1</td>
<td>main_tx_inst2/serializer/n237_s2/I1</td>
</tr>
<tr>
<td>4.399</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>main_tx_inst/serializer/n237_s2/F</td>
<td>22</td>
<td>main_tx_inst2/serializer/n237_s2/F</td>
</tr>
<tr>
<td>5.359</td>
@ -1322,7 +1322,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n400_s12/I2</td>
<td>main_tx_inst2/serializer/n398_s12/I2</td>
</tr>
<tr>
<td>6.181</td>
@ -1330,7 +1330,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n400_s12/F</td>
<td>main_tx_inst2/serializer/n398_s12/F</td>
</tr>
<tr>
<td>7.141</td>
@ -1338,7 +1338,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n400_s10/I1</td>
<td>main_tx_inst2/serializer/n398_s10/I1</td>
</tr>
<tr>
<td>7.290</td>
@ -1346,7 +1346,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n400_s10/O</td>
<td>main_tx_inst2/serializer/n398_s10/O</td>
</tr>
<tr>
<td>8.250</td>
@ -1354,7 +1354,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n400_s5/I1</td>
<td>main_tx_inst2/serializer/n398_s5/I1</td>
</tr>
<tr>
<td>8.413</td>
@ -1362,7 +1362,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/n400_s5/O</td>
<td>main_tx_inst2/serializer/n398_s5/O</td>
</tr>
<tr>
<td>9.373</td>
@ -1370,7 +1370,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_4_s0/D</td>
<td>main_tx_inst2/serializer/ch_out_6_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
@ -1396,7 +1396,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>1.156</td>
<td>tCL</td>
<td>RR</td>
<td>631</td>
<td>1164</td>
<td>pll_main_clock/rpll_inst/CLKOUT</td>
</tr>
<tr>
@ -1405,7 +1405,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_4_s0/CLK</td>
<td>main_tx_inst2/serializer/ch_out_6_s0/CLK</td>
</tr>
<tr>
<td>5.551</td>
@ -1413,7 +1413,7 @@ C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\
<td>tSu</td>
<td> </td>
<td>1</td>
<td>main_tx_inst/serializer/ch_out_4_s0</td>
<td>main_tx_inst2/serializer/ch_out_6_s0</td>
</tr>
</table>
<b>Path Statistics:</b>

72
src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_resource.html
View File

@ -30,7 +30,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">top (C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v)</td>
<td class="label">top (C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">2</td>
@ -40,7 +40,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--pll_main_clock
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
@ -50,7 +50,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--main_rx_1_inst
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
@ -60,7 +60,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--receiver
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
<td align = "center">43</td>
<td align = "center">5</td>
<td align = "center">48</td>
@ -70,17 +70,17 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--clocks
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
<td align = "center">78</td>
<td align = "center">31</td>
<td align = "center">80</td>
<td align = "center">81</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--deserializer
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
<td align = "center">41</td>
<td align = "center">-</td>
<td align = "center">24</td>
@ -90,7 +90,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--demuxer
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
<td align = "center">196</td>
<td align = "center">-</td>
<td align = "center">10</td>
@ -100,7 +100,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--transmitter
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
<td align = "center">210</td>
<td align = "center">-</td>
<td align = "center">121</td>
@ -110,7 +110,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--main_tx_inst
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
@ -120,7 +120,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--clocks
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">99</td>
<td align = "center">93</td>
<td align = "center">39</td>
@ -130,8 +130,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--deserializer
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v)</td>
<td align = "center">406</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">374</td>
<td align = "center">-</td>
<td align = "center">25</td>
<td align = "center">-</td>
@ -140,17 +140,17 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--serializer
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v)</td>
<td align = "center">225</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">210</td>
<td align = "center">-</td>
<td align = "center">109</td>
<td align = "center">103</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--transmitter
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">130</td>
<td align = "center">8</td>
<td align = "center">46</td>
@ -160,7 +160,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--main_tx_inst2
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v)</td>
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
@ -169,11 +169,41 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--transmitter
(C:/sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v)</td>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--clocks
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">99</td>
<td align = "center">93</td>
<td align = "center">39</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--deserializer
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">370</td>
<td align = "center">-</td>
<td align = "center">23</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--serializer
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">210</td>
<td align = "center">-</td>
<td align = "center">103</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp&nbsp|--transmitter
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
<td align = "center">91</td>
<td align = "center">13</td>
<td align = "center">21</td>
<td align = "center">43</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>

19
src/hdl/test_fpga_project/impl/gwsynthesis/test_fpga_project_syn_rsc.xml
View File

@ -1,20 +1,23 @@
<?xml version="1.0" encoding="UTF-8"?>
<Module name="top" Lut="2" T_Register="1527(0)" T_Alu="150(0)" T_Lut="525(2)">
<Module name="top" Lut="2" T_Register="2151(0)" T_Alu="243(0)" T_Lut="707(2)">
<SubModule name="pll_main_clock"/>
<SubModule name="main_rx_1_inst" T_Register="568(0)" T_Alu="36(0)" T_Lut="283(0)">
<SubModule name="main_rx_1_inst" T_Register="568(0)" T_Alu="36(0)" T_Lut="284(0)">
<SubModule name="receiver" Register="43" Alu="5" Lut="48" T_Register="43(43)" T_Alu="5(5)" T_Lut="48(48)"/>
<SubModule name="clocks" Register="78" Alu="31" Lut="80" T_Register="78(78)" T_Alu="31(31)" T_Lut="80(80)"/>
<SubModule name="clocks" Register="78" Alu="31" Lut="81" T_Register="78(78)" T_Alu="31(31)" T_Lut="81(81)"/>
<SubModule name="deserializer" Register="41" Lut="24" T_Register="41(41)" T_Lut="24(24)"/>
<SubModule name="demuxer" Register="196" Lut="10" T_Register="196(196)" T_Lut="10(10)"/>
<SubModule name="transmitter" Register="210" Lut="121" T_Register="210(210)" T_Lut="121(121)"/>
</SubModule>
<SubModule name="main_tx_inst" T_Register="860(0)" T_Alu="101(0)" T_Lut="219(0)">
<SubModule name="main_tx_inst" T_Register="813(0)" T_Alu="101(0)" T_Lut="213(0)">
<SubModule name="clocks" Register="99" Alu="93" Lut="39" T_Register="99(99)" T_Alu="93(93)" T_Lut="39(39)"/>
<SubModule name="deserializer" Register="406" Lut="25" T_Register="406(406)" T_Lut="25(25)"/>
<SubModule name="serializer" Register="225" Lut="109" T_Register="225(225)" T_Lut="109(109)"/>
<SubModule name="deserializer" Register="374" Lut="25" T_Register="374(374)" T_Lut="25(25)"/>
<SubModule name="serializer" Register="210" Lut="103" T_Register="210(210)" T_Lut="103(103)"/>
<SubModule name="transmitter" Register="130" Alu="8" Lut="46" T_Register="130(130)" T_Alu="8(8)" T_Lut="46(46)"/>
</SubModule>
<SubModule name="main_tx_inst2" T_Register="99(0)" T_Alu="13(0)" T_Lut="21(0)">
<SubModule name="transmitter" Register="99" Alu="13" Lut="21" T_Register="99(99)" T_Alu="13(13)" T_Lut="21(21)"/>
<SubModule name="main_tx_inst2" T_Register="770(0)" T_Alu="106(0)" T_Lut="208(0)">
<SubModule name="clocks" Register="99" Alu="93" Lut="39" T_Register="99(99)" T_Alu="93(93)" T_Lut="39(39)"/>
<SubModule name="deserializer" Register="370" Lut="23" T_Register="370(370)" T_Lut="23(23)"/>
<SubModule name="serializer" Register="210" Lut="103" T_Register="210(210)" T_Lut="103(103)"/>
<SubModule name="transmitter" Register="91" Alu="13" Lut="43" T_Register="91(91)" T_Alu="13(13)" T_Lut="43(43)"/>
</SubModule>
</Module>

8
src/hdl/test_fpga_project/impl/pnr/cmd.do
View File

@ -1,9 +1,9 @@
-d C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
-d C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
-p GW1NR-9C-QFN88P-6
-pn GW1NR-LV9QN88PC6/I5
-cst C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst
-cfg C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\pnr\device.cfg
-sdc C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc
-cst C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst
-cfg C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\device.cfg
-sdc C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\test_fpga_project.sdc
-bit
-tr
-ph

2
src/hdl/test_fpga_project/impl/pnr/device.cfg
View File

@ -5,7 +5,6 @@ set READY regular_io = false
set DONE regular_io = true
set I2C regular_io = false
set RECONFIG_N regular_io = false
set unused_pin = default
set CRC_check = true
set compress = false
set encryption = false
@ -20,3 +19,4 @@ set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set vcc = 1.2
set unused_pin = default

BIN
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.bin
View File

Binary file not shown.

BIN
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.binx
View File

Binary file not shown.

BIN
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.db
View File

Binary file not shown.

1194
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.fs
View File

File diff suppressed because it is too large Load Diff

18
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.log
View File

@ -1,7 +1,7 @@
Reading netlist file: "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg"
Parsing netlist file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg" completed
Reading netlist file: "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg"
Parsing netlist file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg" completed
Processing netlist completed
Reading constraint file: "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst"
Reading constraint file: "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
@ -23,10 +23,10 @@ Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\pnr\test_fpga_project.power.html" completed
Generate file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\pnr\test_fpga_project.pin.html" completed
Generate file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\pnr\test_fpga_project.rpt.html" completed
Generate file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\pnr\test_fpga_project.rpt.txt" completed
Generate file "C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\pnr\test_fpga_project.tr.html" completed
Tue Mar 18 23:31:42 2025
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.power.html" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.pin.html" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.html" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.txt" completed
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.tr.html" completed
Sat Oct 4 00:11:09 2025

8
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.pin.html
View File

@ -50,15 +50,15 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\test_fpga_project.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
@ -78,7 +78,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Mar 18 23:31:42 2025
<td>Sat Oct 4 00:11:09 2025
</td>
</tr>
<tr>

96
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.power.html
View File

@ -61,15 +61,15 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\test_fpga_project.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
@ -89,7 +89,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Mar 18 23:31:42 2025
<td>Sat Oct 4 00:11:09 2025
</td>
</tr>
<tr>
@ -161,7 +161,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>37.154</td>
<td>37.476</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
@ -169,7 +169,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>10.618</td>
<td>10.941</td>
</tr>
<tr>
<td class="label">Psram Power (mW)</td>
@ -180,7 +180,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>25.763</td>
<td>25.770</td>
</tr>
<tr>
<td class="label">Theta JA</td>
@ -188,7 +188,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>84.237</td>
<td>84.230</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
@ -203,9 +203,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<tr>
<td>VCC</td>
<td>1.200</td>
<td>6.642</td>
<td>6.911</td>
<td>3.507</td>
<td>12.180</td>
<td>12.503</td>
</tr>
<tr>
<td>VCCX</td>
@ -240,9 +240,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td>Logic</td>
<td>0.603</td>
<td>0.916</td>
<td>NA</td>
<td>16.461</td>
<td>17.883</td>
</tr>
<tr>
<td>IO</td>
@ -266,16 +266,16 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td>top</td>
<td>7.458</td>
<td>7.458(7.457)</td>
<td>7.771</td>
<td>7.771(7.771)</td>
<tr>
<td>top/main_rx_1_inst/</td>
<td>0.226</td>
<td>0.226(0.226)</td>
<tr>
<td>top/main_rx_1_inst/clocks/</td>
<td>0.064</td>
<td>0.064(0.000)</td>
<td>0.065</td>
<td>0.065(0.000)</td>
<tr>
<td>top/main_rx_1_inst/demuxer/</td>
<td>0.037</td>
@ -294,32 +294,44 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<td>0.075(0.000)</td>
<tr>
<td>top/main_tx_inst/</td>
<td>0.366</td>
<td>0.366(0.366)</td>
<td>0.345</td>
<td>0.345(0.345)</td>
<tr>
<td>top/main_tx_inst/clocks/</td>
<td>0.053</td>
<td>0.053(0.000)</td>
<tr>
<td>top/main_tx_inst/deserializer/</td>
<td>0.154</td>
<td>0.154(0.000)</td>
<td>0.143</td>
<td>0.143(0.000)</td>
<tr>
<td>top/main_tx_inst/serializer/</td>
<td>0.147</td>
<td>0.147(0.000)</td>
<td>0.138</td>
<td>0.138(0.000)</td>
<tr>
<td>top/main_tx_inst/transmitter/</td>
<td>0.011</td>
<td>0.011(0.000)</td>
<tr>
<td>top/main_tx_inst2/</td>
<td>0.011</td>
<td>0.011(0.011)</td>
<td>0.344</td>
<td>0.344(0.344)</td>
<tr>
<td>top/main_tx_inst2/clocks/</td>
<td>0.053</td>
<td>0.053(0.000)</td>
<tr>
<td>top/main_tx_inst2/deserializer/</td>
<td>0.141</td>
<td>0.141(0.000)</td>
<tr>
<td>top/main_tx_inst2/serializer/</td>
<td>0.138</td>
<td>0.138(0.000)</td>
<tr>
<td>top/main_tx_inst2/transmitter/</td>
<td>0.011</td>
<td>0.011(0.000)</td>
<td>0.012</td>
<td>0.012(0.000)</td>
<tr>
<td>top/pll_main_clock/</td>
<td>6.855</td>
@ -333,30 +345,30 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>122.880</td>
<td>0.198</td>
</tr>
<tr>
<td>main_rx_1_inst/aes3_bclk</td>
<td>50.000</td>
<td>0.038</td>
</tr>
<tr>
<td>i2s_in_sclk</td>
<td>24.576</td>
<td>6.932</td>
</tr>
<tr>
<td>pll_main_clock/rpll_inst/CLKOUT.default_gen_clk</td>
<td>245.760</td>
<td>0.310</td>
<td>6.987</td>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
<tr>
<td>pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>122.880</td>
<td>0.198</td>
</tr>
<tr>
<td>pll_main_clock/rpll_inst/CLKOUT.default_gen_clk</td>
<td>245.760</td>
<td>0.577</td>
</tr>
<tr>
<td>main_rx_1_inst/aes3_bclk</td>
<td>50.000</td>
<td>0.038</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->

72
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.html
View File

@ -55,15 +55,15 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc</td>
<td>C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\test_fpga_project.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Mar 18 23:31:42 2025
<td>Sat Oct 4 00:11:09 2025
</td>
</tr>
<tr>
@ -97,24 +97,24 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
Placement Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s
Placement Phase 1: CPU time = 0h 0m 0.086s, Elapsed time = 0h 0m 0.086s
Placement Phase 2: CPU time = 0h 0m 0.427s, Elapsed time = 0h 0m 0.427s
Placement Phase 0: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.19s
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.092s
Placement Phase 2: CPU time = 0h 0m 0.747s, Elapsed time = 0h 0m 0.748s
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
Routing Phase 1: CPU time = 0h 0m 0.36s, Elapsed time = 0h 0m 0.36s
Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
Routing Phase 1: CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.561s
Routing Phase 2: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Routing: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s
Generate output files:
CPU time = 0h 0m 0.709s, Elapsed time = 0h 0m 0.708s
CPU time = 0h 0m 0.766s, Elapsed time = 0h 0m 0.765s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 337MB</td>
<td>CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 330MB</td>
</tr>
</table>
<br/>
@ -129,12 +129,12 @@ Generate output files:
</tr>
<tr>
<td class="label">Logic</td>
<td>677/8640</td>
<td>8%</td>
<td>954/8640</td>
<td>12%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>677(519 LUT, 158 ALU, 0 ROM16)</td>
<td>954(700 LUT, 254 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
@ -144,8 +144,8 @@ Generate output files:
</tr>
<tr>
<td class="label">Register</td>
<td>1527/6693</td>
<td>23%</td>
<td>2151/6693</td>
<td>33%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as Latch</td>
@ -154,8 +154,8 @@ Generate output files:
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
<td>1521/6480</td>
<td>24%</td>
<td>2145/6480</td>
<td>34%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as Latch</td>
@ -169,8 +169,8 @@ Generate output files:
</tr>
<tr>
<td class="label">CLS</td>
<td>1054/4320</td>
<td>25%</td>
<td>1491/4320</td>
<td>35%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
@ -227,13 +227,13 @@ Generate output files:
</tr>
<tr>
<td class="label">PRIMARY</td>
<td>4/8</td>
<td>50%</td>
<td>5/8</td>
<td>63%</td>
</tr>
<tr>
<td class="label">LW</td>
<td>7/8</td>
<td>88%</td>
<td>6/8</td>
<td>75%</td>
</tr>
<tr>
<td class="label">GCLK_PIN</td>
@ -262,7 +262,7 @@ Generate output files:
<tr>
<td class="label">clock_200M</td>
<td>PRIMARY</td>
<td> TL BL</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">clock_100M</td>
@ -272,10 +272,15 @@ Generate output files:
<tr>
<td class="label">main_rx_1_inst/aes3_bclk</td>
<td>PRIMARY</td>
<td> BR BL</td>
<td> BR</td>
</tr>
<tr>
<td class="label">n175_10_4</td>
<td class="label">main_tx_inst2/serializer/new_data_pos_edge</td>
<td>PRIMARY</td>
<td> TL BL</td>
</tr>
<tr>
<td class="label">n175_8</td>
<td>LW</td>
<td> -</td>
</tr>
@ -290,17 +295,12 @@ Generate output files:
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/n2035_3</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/n1844_4</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/sample_ch_1_r_buf_23_6</td>
<td class="label">main_tx_inst/deserializer/sample_ch_1_r_buf_21_6</td>
<td>LW</td>
<td> -</td>
</tr>

52
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.rpt.txt
View File

@ -5,34 +5,34 @@
1. PnR Messages
<Report Title>: PnR Report
<Design File>: C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
<Physical Constraints File>: C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst
<Timing Constraints File>: C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc
<Design File>: C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
<Physical Constraints File>: C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.cst
<Timing Constraints File>: C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\test_fpga_project.sdc
<Tool Version>: V1.9.10.03 Education (64-bit)
<Part Number>: GW1NR-LV9QN88PC6/I5
<Device>: GW1NR-9
<Device Version>: C
<Created Time>:Tue Mar 18 23:31:42 2025
<Created Time>:Sat Oct 4 00:11:09 2025
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s
Placement Phase 1: CPU time = 0h 0m 0.086s, Elapsed time = 0h 0m 0.086s
Placement Phase 2: CPU time = 0h 0m 0.427s, Elapsed time = 0h 0m 0.427s
Placement Phase 0: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.19s
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.092s
Placement Phase 2: CPU time = 0h 0m 0.747s, Elapsed time = 0h 0m 0.748s
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
Routing Phase 1: CPU time = 0h 0m 0.36s, Elapsed time = 0h 0m 0.36s
Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
Routing Phase 1: CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.561s
Routing Phase 2: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Routing: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s
Generate output files:
CPU time = 0h 0m 0.709s, Elapsed time = 0h 0m 0.708s
CPU time = 0h 0m 0.766s, Elapsed time = 0h 0m 0.765s
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 337MB
Total Time and Memory Usage: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 330MB
3. Resource Usage Summary
@ -40,15 +40,15 @@
--------------------------------------------------------------------------------
Resources | Usage | Utilization
--------------------------------------------------------------------------------
Logic | 677/8640 | 8%
--LUT,ALU,ROM16 | 677(519 LUT, 158 ALU, 0 ROM16) | -
Logic | 954/8640 | 12%
--LUT,ALU,ROM16 | 954(700 LUT, 254 ALU, 0 ROM16) | -
--SSRAM(RAM16) | 0 | -
Register | 1527/6693 | 23%
Register | 2151/6693 | 33%
--Logic Register as Latch | 0/6480 | 0%
--Logic Register as FF | 1521/6480 | 24%
--Logic Register as FF | 2145/6480 | 34%
--I/O Register as Latch | 0/213 | 0%
--I/O Register as FF | 6/213 | 3%
CLS | 1054/4320 | 25%
CLS | 1491/4320 | 35%
I/O Port | 37/71 | 53%
I/O Buf | 31 | -
--Input Buf | 8 | -
@ -74,8 +74,8 @@
------------------------------------------
Clock Resource| Usage | Utilization
------------------------------------------
PRIMARY | 4/8 | 50%
LW | 7/8 | 88%
PRIMARY | 5/8 | 63%
LW | 6/8 | 75%
GCLK_PIN | 2/3 | 67%
rPLL | 1/2 | 50%
==========================================
@ -87,15 +87,15 @@
Signal | Global Clock | Location
-------------------------------------------
i2s_in_sclk_d | PRIMARY | TR TL BR BL
clock_200M | PRIMARY | TL BL
clock_200M | PRIMARY | TR TL BR BL
clock_100M | PRIMARY | TR TL BR BL
main_rx_1_inst/aes3_bclk| PRIMARY | BR BL
n175_10_4 | LW | -
main_rx_1_inst/aes3_bclk| PRIMARY | BR
main_tx_inst2/serializer/new_data_pos_edge| PRIMARY | TL BL
n175_8 | LW | -
main_rx_1_inst/transmitter/n1680_3| LW | -
main_tx_inst/deserializer/n1658_4| LW | -
main_tx_inst/deserializer/n2035_3| LW | -
main_tx_inst/deserializer/n1844_4| LW | -
main_tx_inst/deserializer/sample_ch_1_r_buf_23_6| LW | -
main_tx_inst/deserializer/sample_ch_1_r_buf_21_6| LW | -
main_tx_inst/serializer/new_data_pos_edge| LW | -
===========================================

1306
src/hdl/test_fpga_project/impl/pnr/test_fpga_project.timing_paths
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File diff suppressed because it is too large Load Diff

2
src/hdl/test_fpga_project/impl/pnr/test_fpga_project_tr_cata.html
View File

@ -48,7 +48,7 @@ function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.
</li>
<!--Setup_Slack_Table end-->
<!--Hold_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="test_fpga_project_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
<li><div class="triangle_fake"></div><a href="test_fpga_project_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;color: #FF0000;" class = "error" target="mainFrame">Hold Paths Table</a>
</li>
<!--Hold_Slack_Table end-->
<!--Recovery_Slack_Table begin-->

13174
src/hdl/test_fpga_project/impl/pnr/test_fpga_project_tr_content.html
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File diff suppressed because it is too large Load Diff

80
src/hdl/test_fpga_project/impl/temp/rtl_parser.result
View File

@ -1,149 +1,149 @@
[
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"InstLine" : 2,
"InstName" : "top",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"ModuleLine" : 2,
"ModuleName" : "top",
"SubInsts" : [
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"InstLine" : 64,
"InstName" : "pll_main_clock",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v",
"ModuleLine" : 10,
"ModuleName" : "gowin_rpll_245"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"InstLine" : 74,
"InstName" : "main_rx_1_inst",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"ModuleLine" : 2,
"ModuleName" : "main_rx",
"SubInsts" : [
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"InstLine" : 24,
"InstName" : "receiver",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3rx.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3rx.vhd",
"ModuleLine" : 14,
"ModuleName" : "aes3rx"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"InstLine" : 40,
"InstName" : "clocks",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_clocks.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_clocks.vhd",
"ModuleLine" : 19,
"ModuleName" : "ultranet_rx_clocks"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"InstLine" : 58,
"InstName" : "deserializer",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_deserializer.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd",
"ModuleLine" : 18,
"ModuleName" : "ultranet_rx_deserializer"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"InstLine" : 83,
"InstName" : "demuxer",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_demux.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
"ModuleLine" : 12,
"ModuleName" : "ultranet_rx_demux"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"InstLine" : 101,
"InstName" : "transmitter",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_transmitter.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_quad_transmitter.vhd",
"ModuleLine" : 11,
"ModuleName" : "i2s_quad_transmitter"
}
]
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"InstLine" : 92,
"InstName" : "main_tx_inst",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"ModuleLine" : 2,
"ModuleName" : "main_tx",
"SubInsts" : [
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 30,
"InstName" : "clocks",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_tx_clocks.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_tx_clocks.vhd",
"ModuleLine" : 6,
"ModuleName" : "ultranet_tx_clocks"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 53,
"InstName" : "deserializer",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_deserializer.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_quad_deserializer.vhd",
"ModuleLine" : 7,
"ModuleName" : "i2s_quad_deserializer"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 82,
"InstName" : "serializer",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_serializer.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_serializer.vhd",
"ModuleLine" : 6,
"ModuleName" : "ultranet_serializer"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 102,
"InstName" : "transmitter",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3tx.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
"ModuleLine" : 11,
"ModuleName" : "aes3tx"
}
]
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"InstLine" : 118,
"InstName" : "main_tx_inst2",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"ModuleLine" : 2,
"ModuleName" : "main_tx",
"SubInsts" : [
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 30,
"InstName" : "clocks",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_tx_clocks.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_tx_clocks.vhd",
"ModuleLine" : 6,
"ModuleName" : "ultranet_tx_clocks"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 53,
"InstName" : "deserializer",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_deserializer.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_quad_deserializer.vhd",
"ModuleLine" : 7,
"ModuleName" : "i2s_quad_deserializer"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 82,
"InstName" : "serializer",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_serializer.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_serializer.vhd",
"ModuleLine" : 6,
"ModuleName" : "ultranet_serializer"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"InstLine" : 102,
"InstName" : "transmitter",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3tx.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
"ModuleLine" : 11,
"ModuleName" : "aes3tx"
}
@ -152,18 +152,18 @@
]
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_deser.vhd",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_deser.vhd",
"InstLine" : 17,
"InstName" : "i2s_deser",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_deser.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_deser.vhd",
"ModuleLine" : 17,
"ModuleName" : "i2s_deser"
},
{
"InstFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/spdif_transmitter.vhd",
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/spdif_transmitter.vhd",
"InstLine" : 12,
"InstName" : "spdif_transmitter",
"ModuleFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/spdif_transmitter.vhd",
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/spdif_transmitter.vhd",
"ModuleLine" : 12,
"ModuleName" : "spdif_transmitter"
}

32
src/hdl/test_fpga_project/impl/temp/rtl_parser_arg.json
View File

@ -2,74 +2,74 @@
"Device" : "GW1NR-9C",
"Files" : [
{
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v",
"Type" : "verilog"
},
{
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main.v",
"Type" : "verilog"
},
{
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
"Type" : "verilog"
},
{
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
"Type" : "verilog"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3rx.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3rx.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3tx.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_deser.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_deser.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_deserializer.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_quad_deserializer.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_transmitter.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_quad_transmitter.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/spdif_transmitter.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/spdif_transmitter.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_clocks.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_clocks.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_demux.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_deserializer.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_serializer.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_serializer.vhd",
"Type" : "vhdl"
},
{
"Library" : "work",
"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_tx_clocks.vhd",
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_tx_clocks.vhd",
"Type" : "vhdl"
}
],
@ -77,7 +77,7 @@
],
"LoopLimit" : 2000,
"ResultFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/impl/temp/rtl_parser.result",
"ResultFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/impl/temp/rtl_parser.result",
"Top" : "top",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"

16
src/hdl/test_fpga_project/src/i2s_quad_deserializer.vhd
View File

@ -148,16 +148,16 @@ begin
-- Output the data
if lrck_pos_edge = '1' then
sample_out_ch_1_r <= sample_ch_1_r_buf;
sample_out_ch_2_r <= sample_ch_2_r_buf;
sample_out_ch_3_r <= sample_ch_3_r_buf;
sample_out_ch_4_r <= sample_ch_4_r_buf;
sample_out_ch_1_r <= sample_ch_1_r_buf(21 downto 0) & "00";
sample_out_ch_2_r <= sample_ch_2_r_buf(21 downto 0) & "01";
sample_out_ch_3_r <= sample_ch_3_r_buf(21 downto 0) & "10";
sample_out_ch_4_r <= sample_ch_4_r_buf(21 downto 0) & "11";
end if;
if lrck_neg_edge = '1' then
sample_out_ch_1_l <= sample_ch_1_l_buf;
sample_out_ch_2_l <= sample_ch_2_l_buf;
sample_out_ch_3_l <= sample_ch_3_l_buf;
sample_out_ch_4_l <= sample_ch_4_l_buf;
sample_out_ch_1_l <= sample_ch_1_l_buf(21 downto 0) & "00";
sample_out_ch_2_l <= sample_ch_2_l_buf(21 downto 0) & "01";
sample_out_ch_3_l <= sample_ch_3_l_buf(21 downto 0) & "10";
sample_out_ch_4_l <= sample_ch_4_l_buf(21 downto 0) & "11";
end if;
end if;
end if;

12
src/hdl/test_fpga_project/src/main.v
View File

@ -103,7 +103,7 @@ main_tx main_tx_inst(
.i2s_in_data_4(i2s_in_data_4),
.aes3_tx(ultranet_tx_1),
.channel_status(384'b000000000000000000000000000000000000000000000000000000000000000011000000111100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.user_status (384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.valid(1'b1),
@ -122,14 +122,14 @@ main_tx main_tx_inst2(
.i2s_in_sclk(i2s_in_sclk),
//.i2s_in_bclk(i2s_in_bclk),
//.i2s_in_lrclk(i2s_in_lrclk),
.i2s_in_data_1(1'b0),
.i2s_in_data_2(1'b0),
.i2s_in_data_3(1'b0),
.i2s_in_data_4(1'b0),
.i2s_in_data_1(i2s_in_data_1),
.i2s_in_data_2(i2s_in_data_2),
.i2s_in_data_3(i2s_in_data_3),
.i2s_in_data_4(i2s_in_data_4),
.aes3_tx(ultranet_tx_2),
.channel_status(384'b000000000000000000000000000000000000000000000000000000000000000011000000111100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.channel_status(384'b000000000000000000000000000000001100000011110011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.user_status (384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.valid(1'b1)
);

2
src/hdl/test_fpga_project/test_fpga_project.gprj.user
View File

@ -22,6 +22,6 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/test_fpga_project_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/test_fpga_project_syn_rsc.xml"/>
</ResultFileList>
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