99 lines
3.7 KiB
Verilog
99 lines
3.7 KiB
Verilog
module main_rx (
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input reset_n, // Active-low reset
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input dir_sclk, // Input DIR system clock (24.576 MHz)
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input dir_bclk, // Input DIR bit clock (12.288 MHz)
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input dir_lrclk, // Input DIR word clock (192 kHz)
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input dir_data, // Input DIR audio data
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input dir_bframe, // Input DIR B-frame indicator
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output i2s_out_sclk, // Output I2S system clock (12.288 MHz)
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output i2s_out_bclk, // Output I2S bit clock (3.072 MHz)
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output i2s_out_lrclk, // Output I2S word clock (48 kHz)
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output i2s_out_data_1, // Output I2S channels 1+2
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output i2s_out_data_2, // Output I2S channels 3+4
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output i2s_out_data_3, // Output I2S channels 5+6
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output i2s_out_data_4 // Output I2S channels 7+8
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);
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// Pulse indicating new set of samples ready
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wire audio_sample_load;
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// Audio sample data wires (24-bit each)
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wire [23:0] audio_sample_1;
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wire [23:0] audio_sample_2;
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wire [23:0] audio_sample_3;
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wire [23:0] audio_sample_4;
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wire [23:0] audio_sample_5;
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wire [23:0] audio_sample_6;
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wire [23:0] audio_sample_7;
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wire [23:0] audio_sample_8;
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// Hypernet receiver / DIR interface: extracts 8 channels of 24-bit samples
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hypernet_rx rx(
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.reset_n(reset_n),
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.bclk(dir_bclk), // Input DIR bit clock (12.288 MHz)
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.lrclk(dir_lrclk), // Input DIR word clock (48 kHz)
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.sdata(dir_data), // Input DIR audio data
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//.bsync(dir_bframe), // Input DIR Frame sync signal
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.ch1_out(audio_sample_1), // Output audio channel 1
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.ch2_out(audio_sample_2), // Output audio channel 2
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.ch3_out(audio_sample_3), // Output audio channel 3
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.ch4_out(audio_sample_4), // Output audio channel 4
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.ch5_out(audio_sample_5), // Output audio channel 5
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.ch6_out(audio_sample_6), // Output audio channel 6
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.ch7_out(audio_sample_7), // Output audio channel 7
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.ch8_out(audio_sample_8), // Output audio channel 8
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.is_end_of_frame(audio_sample_load) // Frame finished, asserted at the end of channel 8
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);
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// Clock divider: generates I2S system clock (12.288 MHz) from AES3 clock (49.152 MHz)
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Gowin_CLKDIV4 sclk_div(
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.hclkin(dir_sclk), // Input recovered clock from the DIR (49.152 MHz)
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.resetn(reset_n),
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.clkout(i2s_out_sclk) // Output I2S system clock (12.288 MHz)
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);
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// I2S clock generator: derives bit and word clocks from I2S system clock and aligns them with the AES3 b-frame signal
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hypernet_synced_i2s_clocks clocks(
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.sclk(i2s_out_sclk), // Input I2S system clock (12.288 MHz)
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.reset_n(reset_n),
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.sync(dir_bframe), // Input AES3 B-Frame signal
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.bclk(i2s_out_bclk), // Output I2S bit clock (3.072 MHz)
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.lrclk(i2s_out_lrclk) // Output I2S word clock (48 kHz)
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);
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// I2S transmitter: converts 8 audio channels into 4 stereo I2S outputs
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i2s_quad_transmitter transmitter(
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.clk(dir_sclk), // Master clock (49.152 MHz) TODO: Rewrite this module to use the I2S system clock
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.reset_n(reset_n),
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.bclk(i2s_out_bclk), // I2S bit clock (3.072 MHz)
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.lrclk(i2s_out_lrclk), // I2S word clock (48 kHz)
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.sample_load(audio_sample_load), // Load new samples when frame ends
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// Map 8 input channels into 4 stereo pairs (L/R)
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.sample_ch_1_l({ audio_sample_1, 8'b00000000}), // Ch1 left (32-bit padded)
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.sample_ch_1_r({ audio_sample_2, 8'b00000000}), // Ch2 right
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.sample_ch_2_l({ audio_sample_3, 8'b00000000}), // Ch3 left
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.sample_ch_2_r({ audio_sample_4, 8'b00000000}), // Ch4 right
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.sample_ch_3_l({ audio_sample_5, 8'b00000000}), // Ch5 left
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.sample_ch_3_r({ audio_sample_6, 8'b00000000}), // Ch6 right
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.sample_ch_4_l({ audio_sample_7, 8'b00000000}), // Ch7 left
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.sample_ch_4_r({ audio_sample_8, 8'b00000000}), // Ch8 right
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// I2S serial outputs for 4 stereo links
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.sdout_1(i2s_out_data_1),
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.sdout_2(i2s_out_data_2),
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.sdout_3(i2s_out_data_3),
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.sdout_4(i2s_out_data_4)
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);
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endmodule |