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HyperNet/src/hdl/impl/gwsynthesis/test_fpga_project_syn_rsc.xml
2025-08-08 12:54:17 +02:00

21 lines
1.5 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<Module name="top" Lut="2" T_Register="1527(0)" T_Alu="150(0)" T_Lut="525(2)">
<SubModule name="pll_main_clock"/>
<SubModule name="main_rx_1_inst" T_Register="568(0)" T_Alu="36(0)" T_Lut="283(0)">
<SubModule name="receiver" Register="43" Alu="5" Lut="48" T_Register="43(43)" T_Alu="5(5)" T_Lut="48(48)"/>
<SubModule name="clocks" Register="78" Alu="31" Lut="80" T_Register="78(78)" T_Alu="31(31)" T_Lut="80(80)"/>
<SubModule name="deserializer" Register="41" Lut="24" T_Register="41(41)" T_Lut="24(24)"/>
<SubModule name="demuxer" Register="196" Lut="10" T_Register="196(196)" T_Lut="10(10)"/>
<SubModule name="transmitter" Register="210" Lut="121" T_Register="210(210)" T_Lut="121(121)"/>
</SubModule>
<SubModule name="main_tx_inst" T_Register="860(0)" T_Alu="101(0)" T_Lut="219(0)">
<SubModule name="clocks" Register="99" Alu="93" Lut="39" T_Register="99(99)" T_Alu="93(93)" T_Lut="39(39)"/>
<SubModule name="deserializer" Register="406" Lut="25" T_Register="406(406)" T_Lut="25(25)"/>
<SubModule name="serializer" Register="225" Lut="109" T_Register="225(225)" T_Lut="109(109)"/>
<SubModule name="transmitter" Register="130" Alu="8" Lut="46" T_Register="130(130)" T_Alu="8(8)" T_Lut="46(46)"/>
</SubModule>
<SubModule name="main_tx_inst2" T_Register="99(0)" T_Alu="13(0)" T_Lut="21(0)">
<SubModule name="transmitter" Register="99" Alu="13" Lut="21" T_Register="99(99)" T_Alu="13(13)" T_Lut="21(21)"/>
</SubModule>
</Module>