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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>PnR Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">PnR Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">PnR Summaries</a></li>-->
<li><a href="#PnR_Details" style=" font-size: 16px;">PnR Details</a>
<li><a href="#Resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#Resource_Usage_Summary" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#I/O_Bank_Usage_Summary" style=" font-size: 14px;">I/O Bank Usage Summary</a></li>
<li><a href="#Global_Clock_Usage_Summary" style=" font-size: 14px;">Clock Resource Usage Summary</a></li>
<li><a href="#Global_Clock_Signals" style=" font-size: 14px;">Global Clock Signals</a></li>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">PnR Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>PnR Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Mar 18 23:31:42 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="PnR_Details">PnR Details</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<table class="summary_table">
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
Placement Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s
Placement Phase 1: CPU time = 0h 0m 0.086s, Elapsed time = 0h 0m 0.086s
Placement Phase 2: CPU time = 0h 0m 0.427s, Elapsed time = 0h 0m 0.427s
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
Routing Phase 1: CPU time = 0h 0m 0.36s, Elapsed time = 0h 0m 0.36s
Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Generate output files:
CPU time = 0h 0m 0.709s, Elapsed time = 0h 0m 0.708s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 337MB</td>
</tr>
</table>
<br/>
<h1><a name="Resource">Resource</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>677/8640</td>
<td>8%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>677(519 LUT, 158 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --SSRAM(RAM16)</td>
<td>0</td>
<td>-</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1527/6693</td>
<td>23%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as Latch</td>
<td>0/6480</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
<td>1521/6480</td>
<td>24%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as Latch</td>
<td>0/213</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as FF</td>
<td>6/213</td>
<td>3%</td>
</tr>
<tr>
<td class="label">CLS</td>
<td>1054/4320</td>
<td>25%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
<td>37/71</td>
<td>53%</td>
</tr>
<tr>
<td class="label">I/O Buf</td>
<td>31</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Input Buf</td>
<td>8</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Output Buf</td>
<td>23</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Inout Buf</td>
<td>0</td>
<td>-</td>
</tr>
</table>
<h2><a name="I/O_Bank_Usage_Summary">I/O Bank Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>I/O Bank</b></td>
<td><b>Usage</b></td><td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">bank 1</td>
<td>11/25</td><td>44%</td>
</tr>
<tr>
<td class="label">bank 2</td>
<td>17/23</td><td>74%</td>
</tr>
<tr>
<td class="label">bank 3</td>
<td>9/23</td><td>40%</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Usage_Summary">Clock Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Clock Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">PRIMARY</td>
<td>4/8</td>
<td>50%</td>
</tr>
<tr>
<td class="label">LW</td>
<td>7/8</td>
<td>88%</td>
</tr>
<tr>
<td class="label">GCLK_PIN</td>
<td>2/3</td>
<td>67%</td>
</tr>
<tr>
<td class="label">rPLL</td>
<td>1/2</td>
<td>50%</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Signal</b></td>
<td><b>Global Clock</b></td>
<td><b>Location</b></td>
</tr>
<tr>
<td class="label">i2s_in_sclk_d</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">clock_200M</td>
<td>PRIMARY</td>
<td> TL BL</td>
</tr>
<tr>
<td class="label">clock_100M</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">main_rx_1_inst/aes3_bclk</td>
<td>PRIMARY</td>
<td> BR BL</td>
</tr>
<tr>
<td class="label">n175_10_4</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_rx_1_inst/transmitter/n1680_3</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/n1658_4</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/n2035_3</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/n1844_4</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/deserializer/sample_ch_1_r_buf_23_6</td>
<td>LW</td>
<td> -</td>
</tr>
<tr>
<td class="label">main_tx_inst/serializer/new_data_pos_edge</td>
<td>LW</td>
<td> -</td>
</tr>
</table>
<br/>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">sys_clk</td>
<td>-</td>
<td>52/1</td>
<td>Y</td>
<td>in</td>
<td>IOR17[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">sys_rst_n</td>
<td>-</td>
<td>4/3</td>
<td>Y</td>
<td>in</td>
<td>IOL5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">aes3_rx</td>
<td>-</td>
<td>28/2</td>
<td>Y</td>
<td>in</td>
<td>IOB11[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">sfp_rx</td>
<td>-</td>
<td>38/2</td>
<td>Y</td>
<td>in</td>
<td>IOB31[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">ultranet_rx_1</td>
<td>-</td>
<td>25/2</td>
<td>Y</td>
<td>in</td>
<td>IOB8[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">ultranet_rx_2</td>
<td>-</td>
<td>39/2</td>
<td>Y</td>
<td>in</td>
<td>IOB33[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_sclk</td>
<td>-</td>
<td>35/2</td>
<td>Y</td>
<td>in</td>
<td>IOB29[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_data_1</td>
<td>-</td>
<td>29/2</td>
<td>Y</td>
<td>in</td>
<td>IOB13[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_data_2</td>
<td>-</td>
<td>30/2</td>
<td>Y</td>
<td>in</td>
<td>IOB13[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_data_3</td>
<td>-</td>
<td>33/2</td>
<td>Y</td>
<td>in</td>
<td>IOB23[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_data_4</td>
<td>-</td>
<td>34/2</td>
<td>Y</td>
<td>in</td>
<td>IOB23[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">key_1</td>
<td>-</td>
<td>79/3</td>
<td>Y</td>
<td>in</td>
<td>IOT12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">key_2</td>
<td>-</td>
<td>77/1</td>
<td>Y</td>
<td>in</td>
<td>IOT37[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">key_3</td>
<td>-</td>
<td>76/1</td>
<td>Y</td>
<td>in</td>
<td>IOT37[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">aes3_tx</td>
<td>-</td>
<td>27/2</td>
<td>Y</td>
<td>out</td>
<td>IOB11[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">sfp_tx</td>
<td>-</td>
<td>37/2</td>
<td>Y</td>
<td>out</td>
<td>IOB31[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">ultranet_tx_1</td>
<td>-</td>
<td>63/1</td>
<td>Y</td>
<td>out</td>
<td>IOR5[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">ultranet_tx_2</td>
<td>-</td>
<td>26/2</td>
<td>Y</td>
<td>out</td>
<td>IOB8[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_out_bclk</td>
<td>-</td>
<td>42/2</td>
<td>Y</td>
<td>out</td>
<td>IOB41[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_out_lrck</td>
<td>-</td>
<td>53/1</td>
<td>Y</td>
<td>out</td>
<td>IOR15[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_out_data_1</td>
<td>-</td>
<td>54/1</td>
<td>Y</td>
<td>out</td>
<td>IOR15[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_out_data_2</td>
<td>-</td>
<td>55/1</td>
<td>Y</td>
<td>out</td>
<td>IOR14[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_out_data_3</td>
<td>-</td>
<td>56/1</td>
<td>Y</td>
<td>out</td>
<td>IOR14[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_out_data_4</td>
<td>-</td>
<td>57/1</td>
<td>Y</td>
<td>out</td>
<td>IOR13[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_bclk</td>
<td>-</td>
<td>41/2</td>
<td>Y</td>
<td>out</td>
<td>IOB41[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i2s_in_lrclk</td>
<td>-</td>
<td>40/2</td>
<td>Y</td>
<td>out</td>
<td>IOB33[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">led_active</td>
<td>-</td>
<td>86/3</td>
<td>Y</td>
<td>out</td>
<td>IOT8[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led_aes3_rx_lock</td>
<td>-</td>
<td>85/3</td>
<td>Y</td>
<td>out</td>
<td>IOT8[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led_aes3_tx</td>
<td>-</td>
<td>84/3</td>
<td>Y</td>
<td>out</td>
<td>IOT10[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led_ultranet_rx1_lock</td>
<td>-</td>
<td>83/3</td>
<td>Y</td>
<td>out</td>
<td>IOT10[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led_ultranet_rx2_lock</td>
<td>-</td>
<td>82/3</td>
<td>Y</td>
<td>out</td>
<td>IOT11[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led_ultranet_tx1</td>
<td>-</td>
<td>81/3</td>
<td>Y</td>
<td>out</td>
<td>IOT11[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led_ultranet_tx2</td>
<td>-</td>
<td>80/3</td>
<td>Y</td>
<td>out</td>
<td>IOT12[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">debug_1</td>
<td>-</td>
<td>48/1</td>
<td>Y</td>
<td>out</td>
<td>IOR24[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">debug_2</td>
<td>-</td>
<td>49/1</td>
<td>Y</td>
<td>out</td>
<td>IOR24[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">debug_3</td>
<td>-</td>
<td>31/2</td>
<td>Y</td>
<td>out</td>
<td>IOB15[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">debug_4</td>
<td>-</td>
<td>32/2</td>
<td>Y</td>
<td>out</td>
<td>IOB15[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<tr>
<td class="label">3/3</td>
<td>-</td>
<td>in</td>
<td>IOT2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">88/3</td>
<td>-</td>
<td>in</td>
<td>IOT5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">87/3</td>
<td>-</td>
<td>in</td>
<td>IOT6[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">86/3</td>
<td>led_active</td>
<td>out</td>
<td>IOT8[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">85/3</td>
<td>led_aes3_rx_lock</td>
<td>out</td>
<td>IOT8[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">84/3</td>
<td>led_aes3_tx</td>
<td>out</td>
<td>IOT10[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">83/3</td>
<td>led_ultranet_rx1_lock</td>
<td>out</td>
<td>IOT10[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">82/3</td>
<td>led_ultranet_rx2_lock</td>
<td>out</td>
<td>IOT11[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">81/3</td>
<td>led_ultranet_tx1</td>
<td>out</td>
<td>IOT11[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">80/3</td>
<td>led_ultranet_tx2</td>
<td>out</td>
<td>IOT12[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">79/3</td>
<td>key_1</td>
<td>in</td>
<td>IOT12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">77/1</td>
<td>key_2</td>
<td>in</td>
<td>IOT37[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">76/1</td>
<td>key_3</td>
<td>in</td>
<td>IOT37[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">75/1</td>
<td>-</td>
<td>in</td>
<td>IOT38[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">74/1</td>
<td>-</td>
<td>in</td>
<td>IOT38[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">73/1</td>
<td>-</td>
<td>in</td>
<td>IOT39[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">72/1</td>
<td>-</td>
<td>in</td>
<td>IOT39[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">71/1</td>
<td>-</td>
<td>in</td>
<td>IOT41[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">70/1</td>
<td>-</td>
<td>in</td>
<td>IOT41[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">69/1</td>
<td>-</td>
<td>in</td>
<td>IOT42[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">68/1</td>
<td>-</td>
<td>in</td>
<td>IOT42[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">17/2</td>
<td>-</td>
<td>in</td>
<td>IOB2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">18/2</td>
<td>-</td>
<td>in</td>
<td>IOB2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">19/2</td>
<td>-</td>
<td>in</td>
<td>IOB4[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">20/2</td>
<td>-</td>
<td>in</td>
<td>IOB4[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">25/2</td>
<td>ultranet_rx_1</td>
<td>in</td>
<td>IOB8[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">26/2</td>
<td>ultranet_tx_2</td>
<td>out</td>
<td>IOB8[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">27/2</td>
<td>aes3_tx</td>
<td>out</td>
<td>IOB11[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">28/2</td>
<td>aes3_rx</td>
<td>in</td>
<td>IOB11[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">29/2</td>
<td>i2s_in_data_1</td>
<td>in</td>
<td>IOB13[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">30/2</td>
<td>i2s_in_data_2</td>
<td>in</td>
<td>IOB13[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">31/2</td>
<td>debug_3</td>
<td>out</td>
<td>IOB15[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">32/2</td>
<td>debug_4</td>
<td>out</td>
<td>IOB15[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">33/2</td>
<td>i2s_in_data_3</td>
<td>in</td>
<td>IOB23[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">34/2</td>
<td>i2s_in_data_4</td>
<td>in</td>
<td>IOB23[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">35/2</td>
<td>i2s_in_sclk</td>
<td>in</td>
<td>IOB29[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">36/2</td>
<td>-</td>
<td>in</td>
<td>IOB29[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">37/2</td>
<td>sfp_tx</td>
<td>out</td>
<td>IOB31[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">38/2</td>
<td>sfp_rx</td>
<td>in</td>
<td>IOB31[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">39/2</td>
<td>ultranet_rx_2</td>
<td>in</td>
<td>IOB33[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">40/2</td>
<td>i2s_in_lrclk</td>
<td>out</td>
<td>IOB33[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">41/2</td>
<td>i2s_in_bclk</td>
<td>out</td>
<td>IOB41[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">42/2</td>
<td>i2s_out_bclk</td>
<td>out</td>
<td>IOB41[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">47/2</td>
<td>-</td>
<td>in</td>
<td>IOB43[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">4/3</td>
<td>sys_rst_n</td>
<td>in</td>
<td>IOL5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">5/3</td>
<td>-</td>
<td>in</td>
<td>IOL11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">6/3</td>
<td>-</td>
<td>in</td>
<td>IOL11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">7/3</td>
<td>-</td>
<td>in</td>
<td>IOL12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">8/3</td>
<td>-</td>
<td>out</td>
<td>IOL13[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">9/3</td>
<td>-</td>
<td>in</td>
<td>IOL13[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">10/3</td>
<td>-</td>
<td>in</td>
<td>IOL15[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">11/3</td>
<td>-</td>
<td>in</td>
<td>IOL16[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">13/3</td>
<td>-</td>
<td>in</td>
<td>IOL21[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">14/3</td>
<td>-</td>
<td>in</td>
<td>IOL22[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">15/3</td>
<td>-</td>
<td>in</td>
<td>IOL25[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">16/3</td>
<td>-</td>
<td>in</td>
<td>IOL26[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">63/1</td>
<td>ultranet_tx_1</td>
<td>out</td>
<td>IOR5[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">62/1</td>
<td>-</td>
<td>in</td>
<td>IOR11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">61/1</td>
<td>-</td>
<td>in</td>
<td>IOR11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">60/1</td>
<td>-</td>
<td>in</td>
<td>IOR12[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">59/1</td>
<td>-</td>
<td>in</td>
<td>IOR12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">57/1</td>
<td>i2s_out_data_4</td>
<td>out</td>
<td>IOR13[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">56/1</td>
<td>i2s_out_data_3</td>
<td>out</td>
<td>IOR14[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">55/1</td>
<td>i2s_out_data_2</td>
<td>out</td>
<td>IOR14[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">54/1</td>
<td>i2s_out_data_1</td>
<td>out</td>
<td>IOR15[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">53/1</td>
<td>i2s_out_lrck</td>
<td>out</td>
<td>IOR15[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">52/1</td>
<td>sys_clk</td>
<td>in</td>
<td>IOR17[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">51/1</td>
<td>-</td>
<td>in</td>
<td>IOR17[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">50/1</td>
<td>-</td>
<td>in</td>
<td>IOR22[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">49/1</td>
<td>debug_2</td>
<td>out</td>
<td>IOR24[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">48/1</td>
<td>debug_1</td>
<td>out</td>
<td>IOR24[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
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