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HyperNet/src/hdl/impl/pnr/test_fpga_project.rpt.txt
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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\impl\gwsynthesis\test_fpga_project.vg
<Physical Constraints File>: C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\main.cst
<Timing Constraints File>: C:\sdk\Gowin\Gowin_V1.9.10.03_Education_x64\IDE\bin\Documents\test_fpga_project\src\test_fpga_project.sdc
<Tool Version>: V1.9.10.03 Education (64-bit)
<Part Number>: GW1NR-LV9QN88PC6/I5
<Device>: GW1NR-9
<Device Version>: C
<Created Time>:Tue Mar 18 23:31:42 2025
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s
Placement Phase 1: CPU time = 0h 0m 0.086s, Elapsed time = 0h 0m 0.086s
Placement Phase 2: CPU time = 0h 0m 0.427s, Elapsed time = 0h 0m 0.427s
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
Routing Phase 1: CPU time = 0h 0m 0.36s, Elapsed time = 0h 0m 0.36s
Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Generate output files:
CPU time = 0h 0m 0.709s, Elapsed time = 0h 0m 0.708s
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 337MB
3. Resource Usage Summary
--------------------------------------------------------------------------------
Resources | Usage | Utilization
--------------------------------------------------------------------------------
Logic | 677/8640 | 8%
--LUT,ALU,ROM16 | 677(519 LUT, 158 ALU, 0 ROM16) | -
--SSRAM(RAM16) | 0 | -
Register | 1527/6693 | 23%
--Logic Register as Latch | 0/6480 | 0%
--Logic Register as FF | 1521/6480 | 24%
--I/O Register as Latch | 0/213 | 0%
--I/O Register as FF | 6/213 | 3%
CLS | 1054/4320 | 25%
I/O Port | 37/71 | 53%
I/O Buf | 31 | -
--Input Buf | 8 | -
--Output Buf | 23 | -
--Inout Buf | 0 | -
================================================================================
4. I/O Bank Usage Summary
--------------------------------------
I/O Bank | Usage | Utilization
--------------------------------------
bank 1 | 11/25 | 44%
bank 2 | 17/23 | 74%
bank 3 | 9/23 | 40%
======================================
5. Clock Resource Usage Summary
------------------------------------------
Clock Resource| Usage | Utilization
------------------------------------------
PRIMARY | 4/8 | 50%
LW | 7/8 | 88%
GCLK_PIN | 2/3 | 67%
rPLL | 1/2 | 50%
==========================================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
i2s_in_sclk_d | PRIMARY | TR TL BR BL
clock_200M | PRIMARY | TL BL
clock_100M | PRIMARY | TR TL BR BL
main_rx_1_inst/aes3_bclk| PRIMARY | BR BL
n175_10_4 | LW | -
main_rx_1_inst/transmitter/n1680_3| LW | -
main_tx_inst/deserializer/n1658_4| LW | -
main_tx_inst/deserializer/n2035_3| LW | -
main_tx_inst/deserializer/n1844_4| LW | -
main_tx_inst/deserializer/sample_ch_1_r_buf_23_6| LW | -
main_tx_inst/serializer/new_data_pos_edge| LW | -
===========================================
7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
sys_clk | - | 52/1 | Y | in | IOR17[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3
sys_rst_n | - | 4/3 | Y | in | IOL5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
aes3_rx | - | 28/2 | Y | in | IOB11[B] | LVCMOS33 | NA | NONE | OFF | NONE | NA | NA | NA | NA | 3.3
sfp_rx | - | 38/2 | Y | in | IOB31[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
ultranet_rx_1 | - | 25/2 | Y | in | IOB8[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
ultranet_rx_2 | - | 39/2 | Y | in | IOB33[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
i2s_in_sclk | - | 35/2 | Y | in | IOB29[A] | LVCMOS33 | NA | NONE | OFF | NONE | NA | NA | NA | NA | 3.3
i2s_in_data_1 | - | 29/2 | Y | in | IOB13[A] | LVCMOS33 | NA | NONE | OFF | NONE | NA | NA | NA | NA | 3.3
i2s_in_data_2 | - | 30/2 | Y | in | IOB13[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
i2s_in_data_3 | - | 33/2 | Y | in | IOB23[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
i2s_in_data_4 | - | 34/2 | Y | in | IOB23[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
key_1 | - | 79/3 | Y | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
key_2 | - | 77/1 | Y | in | IOT37[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3
key_3 | - | 76/1 | Y | in | IOT37[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3
aes3_tx | - | 27/2 | Y | out | IOB11[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
sfp_tx | - | 37/2 | Y | out | IOB31[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
ultranet_tx_1 | - | 63/1 | Y | out | IOR5[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
ultranet_tx_2 | - | 26/2 | Y | out | IOB8[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
i2s_out_bclk | - | 42/2 | Y | out | IOB41[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
i2s_out_lrck | - | 53/1 | Y | out | IOR15[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
i2s_out_data_1 | - | 54/1 | Y | out | IOR15[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
i2s_out_data_2 | - | 55/1 | Y | out | IOR14[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
i2s_out_data_3 | - | 56/1 | Y | out | IOR14[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
i2s_out_data_4 | - | 57/1 | Y | out | IOR13[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
i2s_in_bclk | - | 41/2 | Y | out | IOB41[A] | LVCMOS33 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 3.3
i2s_in_lrclk | - | 40/2 | Y | out | IOB33[B] | LVCMOS33 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 3.3
led_active | - | 86/3 | Y | out | IOT8[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
led_aes3_rx_lock | - | 85/3 | Y | out | IOT8[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
led_aes3_tx | - | 84/3 | Y | out | IOT10[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
led_ultranet_rx1_lock | - | 83/3 | Y | out | IOT10[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
led_ultranet_rx2_lock | - | 82/3 | Y | out | IOT11[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
led_ultranet_tx1 | - | 81/3 | Y | out | IOT11[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
led_ultranet_tx2 | - | 80/3 | Y | out | IOT12[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
debug_1 | - | 48/1 | Y | out | IOR24[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
debug_2 | - | 49/1 | Y | out | IOR24[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
debug_3 | - | 31/2 | Y | out | IOB15[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
debug_4 | - | 32/2 | Y | out | IOB15[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
==============================================================================================================================================================================================================================
8. All Package Pins
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
3/3 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
88/3 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
87/3 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
86/3 | led_active | out | IOT8[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
85/3 | led_aes3_rx_lock | out | IOT8[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
84/3 | led_aes3_tx | out | IOT10[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
83/3 | led_ultranet_rx1_lock | out | IOT10[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
82/3 | led_ultranet_rx2_lock | out | IOT11[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
81/3 | led_ultranet_tx1 | out | IOT11[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
80/3 | led_ultranet_tx2 | out | IOT12[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
79/3 | key_1 | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
77/1 | key_2 | in | IOT37[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3
76/1 | key_3 | in | IOT37[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3
75/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
74/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
73/1 | - | in | IOT39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
72/1 | - | in | IOT39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
71/1 | - | in | IOT41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
70/1 | - | in | IOT41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
69/1 | - | in | IOT42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
68/1 | - | in | IOT42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
17/2 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
18/2 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
19/2 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
20/2 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
25/2 | ultranet_rx_1 | in | IOB8[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
26/2 | ultranet_tx_2 | out | IOB8[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
27/2 | aes3_tx | out | IOB11[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
28/2 | aes3_rx | in | IOB11[B] | LVCMOS33 | NA | NONE | OFF | NONE | NA | NA | NA | NA | 3.3
29/2 | i2s_in_data_1 | in | IOB13[A] | LVCMOS33 | NA | NONE | OFF | NONE | NA | NA | NA | NA | 3.3
30/2 | i2s_in_data_2 | in | IOB13[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
31/2 | debug_3 | out | IOB15[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
32/2 | debug_4 | out | IOB15[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
33/2 | i2s_in_data_3 | in | IOB23[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
34/2 | i2s_in_data_4 | in | IOB23[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
35/2 | i2s_in_sclk | in | IOB29[A] | LVCMOS33 | NA | NONE | OFF | NONE | NA | NA | NA | NA | 3.3
36/2 | - | in | IOB29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
37/2 | sfp_tx | out | IOB31[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
38/2 | sfp_rx | in | IOB31[B] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
39/2 | ultranet_rx_2 | in | IOB33[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
40/2 | i2s_in_lrclk | out | IOB33[B] | LVCMOS33 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 3.3
41/2 | i2s_in_bclk | out | IOB41[A] | LVCMOS33 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 3.3
42/2 | i2s_out_bclk | out | IOB41[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | NA | NA | 3.3
47/2 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
4/3 | sys_rst_n | in | IOL5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
5/3 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
6/3 | - | in | IOL11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
7/3 | - | in | IOL12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
8/3 | - | out | IOL13[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
9/3 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
10/3 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
11/3 | - | in | IOL16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
13/3 | - | in | IOL21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
14/3 | - | in | IOL22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
15/3 | - | in | IOL25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
16/3 | - | in | IOL26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
63/1 | ultranet_tx_1 | out | IOR5[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
62/1 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
61/1 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
60/1 | - | in | IOR12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
59/1 | - | in | IOR12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
57/1 | i2s_out_data_4 | out | IOR13[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
56/1 | i2s_out_data_3 | out | IOR14[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
55/1 | i2s_out_data_2 | out | IOR14[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
54/1 | i2s_out_data_1 | out | IOR15[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
53/1 | i2s_out_lrck | out | IOR15[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
52/1 | sys_clk | in | IOR17[A] | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3
51/1 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
50/1 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3
49/1 | debug_2 | out | IOR24[A] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
48/1 | debug_1 | out | IOR24[B] | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
===================================================================================================================================================================================================
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