84 lines
2.7 KiB
JSON
84 lines
2.7 KiB
JSON
{
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"Device" : "GW1NR-9C",
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"Files" : [
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{
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/gowin_rpll/gowin_rpll_245.v.v",
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"Type" : "verilog"
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},
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{
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main.v",
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"Type" : "verilog"
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},
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{
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_rx.v",
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"Type" : "verilog"
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},
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{
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/main_tx.v",
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"Type" : "verilog"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3rx.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/aes3tx.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_deser.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_deserializer.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/i2s_quad_transmitter.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/spdif_transmitter.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_clocks.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_demux.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_rx_deserializer.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_serializer.vhd",
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"Type" : "vhdl"
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},
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{
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"Library" : "work",
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"Path" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/src/ultranet_tx_clocks.vhd",
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"Type" : "vhdl"
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}
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],
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"IncludePath" : [
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],
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"LoopLimit" : 2000,
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"ResultFile" : "C:/Sdk/Gowin/Gowin_V1.9.10.03_Education_x64/IDE/bin/Documents/test_fpga_project/impl/temp/rtl_parser.result",
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"Top" : "top",
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"VerilogStd" : "verilog_2001",
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"VhdlStd" : "vhdl_93"
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} |