Rewrote ultranet_rx_demux to sync&use the channel index the sample data
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c641559228
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C97F759321C4C29C
@ -25,19 +25,19 @@ Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\te
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd'
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Analyzing entity 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":37)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd'
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Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":12)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":36)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd'
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Analyzing entity 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":45)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":44)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd'
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Analyzing entity 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":26)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd'
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Analyzing entity 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":18)
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WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":136)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd'
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Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":30)
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WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":135)
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Compiling module 'top'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":2)
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Compiling module 'gowin_rpll_245'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10)
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Compiling module 'main_rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":2)
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@ -47,15 +47,16 @@ Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\H
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Switching to VHDL mode to elaborate design unit 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":50)
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Processing 'ultranet_rx_clocks(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":50)
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Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":70)
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Switching to VHDL mode to elaborate design unit 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":68)
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Processing 'ultranet_rx_deserializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":70)
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Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":98)
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Processing 'ultranet_rx_demux(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":12)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":98)
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Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":121)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":68)
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Switching to VHDL mode to elaborate design unit 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":95)
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Processing 'ultranet_rx_demux(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6)
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'others' clause is never selected("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":81)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":95)
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Switching to VHDL mode to elaborate design unit 'i2s_quad_transmitter'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":118)
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Processing 'i2s_quad_transmitter(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd":11)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":121)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":118)
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Compiling module 'main_tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":2)
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Switching to VHDL mode to elaborate design unit 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":38)
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Processing 'ultranet_tx_clocks(Behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
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@ -15,10 +15,10 @@
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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File diff suppressed because it is too large
Load Diff
@ -66,10 +66,10 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_dese
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd<br>
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C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd<br>
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</td>
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</tr>
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<tr>
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@ -94,7 +94,7 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Sat Oct 4 00:10:56 2025
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<td>Sat Oct 4 16:56:17 2025
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</td>
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</tr>
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<tr>
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@ -110,11 +110,11 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label">Synthesis Process</td>
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<td>Running parser:<br/> CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 330.844MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.239s, Peak memory usage = 330.844MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 330.844MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 330.844MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 330.844MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 330.844MB<br/> Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 330.844MB<br/> Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 330.844MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 330.844MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 330.844MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 330.844MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 330.844MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 330.844MB<br/>Generate output files:<br/> CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 330.844MB<br/></td>
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<td>Running parser:<br/> CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.377s, Peak memory usage = 332.207MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 332.207MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 332.207MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.323s, Peak memory usage = 332.207MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 332.207MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 332.207MB<br/> Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 332.207MB<br/> Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 332.207MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 332.207MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 332.207MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 332.207MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 332.207MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 332.207MB<br/>Generate output files:<br/> CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 332.207MB<br/></td>
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</tr>
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<tr>
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<td class="label">Total Time and Memory Usage</td>
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<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 330.844MB</td>
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<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 332.207MB</td>
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</tr>
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</table>
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<h1><a name="resource">Resource</a></h1>
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@ -146,23 +146,23 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label"><b>Register </b></td>
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<td>2151</td>
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<td>2313</td>
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</tr>
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<tr>
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<td class="label">    DFF</td>
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<td>81</td>
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<td>73</td>
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</tr>
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<tr>
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<td class="label">    DFFE</td>
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<td>1570</td>
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<td>1743</td>
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</tr>
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<tr>
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<td class="label">    DFFS</td>
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<td>3</td>
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<td>2</td>
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</tr>
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<tr>
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<td class="label">    DFFSE</td>
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<td>35</td>
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<td>36</td>
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</tr>
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<tr>
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<td class="label">    DFFR</td>
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@ -170,23 +170,23 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label">    DFFRE</td>
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<td>193</td>
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<td>190</td>
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</tr>
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<tr>
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<td class="label"><b>LUT </b></td>
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<td>676</td>
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<td>661</td>
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</tr>
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<tr>
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<td class="label">    LUT2</td>
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<td>66</td>
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<td>67</td>
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</tr>
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<tr>
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<td class="label">    LUT3</td>
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<td>391</td>
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<td>371</td>
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</tr>
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<tr>
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<td class="label">    LUT4</td>
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<td>219</td>
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<td>223</td>
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</tr>
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<tr>
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<td class="label"><b>ALU </b></td>
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@ -198,11 +198,11 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label"><b>INV </b></td>
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<td>31</td>
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<td>34</td>
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</tr>
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<tr>
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<td class="label">    INV</td>
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<td>31</td>
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<td>34</td>
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</tr>
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<tr>
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<td class="label"><b>CLOCK </b></td>
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@ -222,13 +222,13 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label">Logic</td>
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<td>950(707 LUT, 243 ALU) / 8640</td>
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<td>938(695 LUT, 243 ALU) / 8640</td>
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<td>11%</td>
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</tr>
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<tr>
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<td class="label">Register</td>
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<td>2151 / 6693</td>
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<td>33%</td>
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<td>2313 / 6693</td>
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<td>35%</td>
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</tr>
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<tr>
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<td class="label">  --Register as Latch</td>
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@ -237,8 +237,8 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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</tr>
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<tr>
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<td class="label">  --Register as FF</td>
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<td>2151 / 6693</td>
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<td>33%</td>
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<td>2313 / 6693</td>
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<td>35%</td>
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</tr>
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<tr>
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<td class="label">BSRAM</td>
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@ -348,7 +348,7 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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<td>1</td>
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<td>i2s_in_sclk</td>
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<td>24.576(MHz)</td>
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<td>82.841(MHz)</td>
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<td>84.308(MHz)</td>
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<td>5</td>
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<td>TOP</td>
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</tr>
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@ -356,8 +356,8 @@ C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_c
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<td>2</td>
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<td>main_rx_1_inst/receiver/aes3_bclk</td>
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<td>50.000(MHz)</td>
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<td>125.073(MHz)</td>
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<td>4</td>
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<td>111.699(MHz)</td>
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<td>5</td>
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<td>TOP</td>
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</tr>
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<tr>
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@ -63,7 +63,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
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<td align = "center">43</td>
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<td align = "center">5</td>
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<td align = "center">48</td>
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<td align = "center">47</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -81,9 +81,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
|
||||
</tr>
|
||||
<td class="label">        |--deserializer
|
||||
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
|
||||
<td align = "center">41</td>
|
||||
<td align = "center">38</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">24</td>
|
||||
<td align = "center">20</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
@ -91,9 +91,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
|
||||
</tr>
|
||||
<td class="label">        |--demuxer
|
||||
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
|
||||
<td align = "center">196</td>
|
||||
<td align = "center">377</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">10</td>
|
||||
<td align = "center">7</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
@ -101,9 +101,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
|
||||
</tr>
|
||||
<td class="label">        |--transmitter
|
||||
(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
|
||||
<td align = "center">210</td>
|
||||
<td align = "center">194</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">121</td>
|
||||
<td align = "center">117</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="top" Lut="2" T_Register="2151(0)" T_Alu="243(0)" T_Lut="707(2)">
|
||||
<Module name="top" Lut="2" T_Register="2313(0)" T_Alu="243(0)" T_Lut="695(2)">
|
||||
<SubModule name="pll_main_clock"/>
|
||||
<SubModule name="main_rx_1_inst" T_Register="568(0)" T_Alu="36(0)" T_Lut="284(0)">
|
||||
<SubModule name="receiver" Register="43" Alu="5" Lut="48" T_Register="43(43)" T_Alu="5(5)" T_Lut="48(48)"/>
|
||||
<SubModule name="main_rx_1_inst" T_Register="730(0)" T_Alu="36(0)" T_Lut="272(0)">
|
||||
<SubModule name="receiver" Register="43" Alu="5" Lut="47" T_Register="43(43)" T_Alu="5(5)" T_Lut="47(47)"/>
|
||||
<SubModule name="clocks" Register="78" Alu="31" Lut="81" T_Register="78(78)" T_Alu="31(31)" T_Lut="81(81)"/>
|
||||
<SubModule name="deserializer" Register="41" Lut="24" T_Register="41(41)" T_Lut="24(24)"/>
|
||||
<SubModule name="demuxer" Register="196" Lut="10" T_Register="196(196)" T_Lut="10(10)"/>
|
||||
<SubModule name="transmitter" Register="210" Lut="121" T_Register="210(210)" T_Lut="121(121)"/>
|
||||
<SubModule name="deserializer" Register="38" Lut="20" T_Register="38(38)" T_Lut="20(20)"/>
|
||||
<SubModule name="demuxer" Register="377" Lut="7" T_Register="377(377)" T_Lut="7(7)"/>
|
||||
<SubModule name="transmitter" Register="194" Lut="117" T_Register="194(194)" T_Lut="117(117)"/>
|
||||
</SubModule>
|
||||
<SubModule name="main_tx_inst" T_Register="813(0)" T_Alu="101(0)" T_Lut="213(0)">
|
||||
<SubModule name="clocks" Register="99" Alu="93" Lut="39" T_Register="99(99)" T_Alu="93(93)" T_Lut="39(39)"/>
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -28,5 +28,5 @@ Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\p
|
||||
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.html" completed
|
||||
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.txt" completed
|
||||
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.tr.html" completed
|
||||
Sat Oct 4 00:11:09 2025
|
||||
Sat Oct 4 16:56:29 2025
|
||||
|
||||
|
||||
@ -78,7 +78,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Oct 4 00:11:09 2025
|
||||
<td>Sat Oct 4 16:56:29 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
||||
@ -89,7 +89,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Oct 4 00:11:09 2025
|
||||
<td>Sat Oct 4 16:56:29 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -161,7 +161,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Total Power (mW)</td>
|
||||
<td>37.476</td>
|
||||
<td>37.498</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Quiescent Power (mW)</td>
|
||||
@ -169,7 +169,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Dynamic Power (mW)</td>
|
||||
<td>10.941</td>
|
||||
<td>10.963</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Psram Power (mW)</td>
|
||||
@ -203,9 +203,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<tr>
|
||||
<td>VCC</td>
|
||||
<td>1.200</td>
|
||||
<td>6.911</td>
|
||||
<td>6.930</td>
|
||||
<td>3.507</td>
|
||||
<td>12.503</td>
|
||||
<td>12.525</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCX</td>
|
||||
@ -240,9 +240,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Logic</td>
|
||||
<td>0.916</td>
|
||||
<td>0.940</td>
|
||||
<td>NA</td>
|
||||
<td>17.883</td>
|
||||
<td>17.770</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>IO</td>
|
||||
@ -266,32 +266,32 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td>top</td>
|
||||
<td>7.771</td>
|
||||
<td>7.771(7.771)</td>
|
||||
<td>7.795</td>
|
||||
<td>7.795(7.795)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/</td>
|
||||
<td>0.226</td>
|
||||
<td>0.226(0.226)</td>
|
||||
<td>0.250</td>
|
||||
<td>0.250(0.250)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/clocks/</td>
|
||||
<td>0.065</td>
|
||||
<td>0.065(0.000)</td>
|
||||
<td>0.064</td>
|
||||
<td>0.064(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/demuxer/</td>
|
||||
<td>0.037</td>
|
||||
<td>0.037(0.000)</td>
|
||||
<td>0.067</td>
|
||||
<td>0.067(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/deserializer/</td>
|
||||
<td>0.015</td>
|
||||
<td>0.015(0.000)</td>
|
||||
<td>0.013</td>
|
||||
<td>0.013(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/receiver/</td>
|
||||
<td>0.035</td>
|
||||
<td>0.035(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/transmitter/</td>
|
||||
<td>0.075</td>
|
||||
<td>0.075(0.000)</td>
|
||||
<td>0.071</td>
|
||||
<td>0.071(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/</td>
|
||||
<td>0.345</td>
|
||||
@ -345,19 +345,19 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<th class="label">Total Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>i2s_in_sclk</td>
|
||||
<td>24.576</td>
|
||||
<td>6.987</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NO CLOCK DOMAIN</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>i2s_in_sclk</td>
|
||||
<td>24.576</td>
|
||||
<td>6.987</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk</td>
|
||||
<td>122.880</td>
|
||||
<td>0.198</td>
|
||||
<td>0.220</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>pll_main_clock/rpll_inst/CLKOUT.default_gen_clk</td>
|
||||
|
||||
@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Oct 4 00:11:09 2025
|
||||
<td>Sat Oct 4 16:56:29 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -97,24 +97,24 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<tr>
|
||||
<td class="label">Place & Route Process</td>
|
||||
<td>Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.19s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.092s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.747s, Elapsed time = 0h 0m 0.748s
|
||||
Placement Phase 0: CPU time = 0h 0m 0.204s, Elapsed time = 0h 0m 0.204s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.091s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.741s, Elapsed time = 0h 0m 0.741s
|
||||
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.561s
|
||||
Routing Phase 2: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.615s, Elapsed time = 0h 0m 0.616s
|
||||
Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s
|
||||
Total Routing: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 0.766s, Elapsed time = 0h 0m 0.765s
|
||||
CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.734s
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 330MB</td>
|
||||
<td>CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 332MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<br/>
|
||||
@ -129,12 +129,12 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>954/8640</td>
|
||||
<td>12%</td>
|
||||
<td>943/8640</td>
|
||||
<td>11%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --LUT,ALU,ROM16</td>
|
||||
<td>954(700 LUT, 254 ALU, 0 ROM16)</td>
|
||||
<td>943(689 LUT, 254 ALU, 0 ROM16)</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -144,8 +144,8 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>2151/6693</td>
|
||||
<td>33%</td>
|
||||
<td>2313/6693</td>
|
||||
<td>35%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --Logic Register as Latch</td>
|
||||
@ -154,8 +154,8 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --Logic Register as FF</td>
|
||||
<td>2145/6480</td>
|
||||
<td>34%</td>
|
||||
<td>2307/6480</td>
|
||||
<td>36%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --I/O Register as Latch</td>
|
||||
@ -169,8 +169,8 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">CLS</td>
|
||||
<td>1491/4320</td>
|
||||
<td>35%</td>
|
||||
<td>1574/4320</td>
|
||||
<td>37%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">I/O Port</td>
|
||||
@ -227,13 +227,13 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">PRIMARY</td>
|
||||
<td>5/8</td>
|
||||
<td>63%</td>
|
||||
<td>4/8</td>
|
||||
<td>50%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">LW</td>
|
||||
<td>6/8</td>
|
||||
<td>75%</td>
|
||||
<td>7/8</td>
|
||||
<td>88%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GCLK_PIN</td>
|
||||
@ -267,7 +267,7 @@ Generate output files:
|
||||
<tr>
|
||||
<td class="label">clock_100M</td>
|
||||
<td>PRIMARY</td>
|
||||
<td> TR TL BR BL</td>
|
||||
<td> TR BR BL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_rx_1_inst/aes3_bclk</td>
|
||||
@ -275,12 +275,12 @@ Generate output files:
|
||||
<td> BR</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst2/serializer/new_data_pos_edge</td>
|
||||
<td>PRIMARY</td>
|
||||
<td> TL BL</td>
|
||||
<td class="label">n175_8</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">n175_8</td>
|
||||
<td class="label">main_rx_1_inst/demuxer/new_data_re</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
@ -300,12 +300,12 @@ Generate output files:
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst/deserializer/sample_ch_1_r_buf_21_6</td>
|
||||
<td class="label">main_tx_inst/serializer/new_data_pos_edge</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst/serializer/new_data_pos_edge</td>
|
||||
<td class="label">main_tx_inst2/serializer/new_data_pos_edge</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
|
||||
@ -12,27 +12,27 @@
|
||||
<Part Number>: GW1NR-LV9QN88PC6/I5
|
||||
<Device>: GW1NR-9
|
||||
<Device Version>: C
|
||||
<Created Time>:Sat Oct 4 00:11:09 2025
|
||||
<Created Time>:Sat Oct 4 16:56:29 2025
|
||||
|
||||
|
||||
2. PnR Details
|
||||
|
||||
Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.19s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.092s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.747s, Elapsed time = 0h 0m 0.748s
|
||||
Placement Phase 0: CPU time = 0h 0m 0.204s, Elapsed time = 0h 0m 0.204s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.091s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.741s, Elapsed time = 0h 0m 0.741s
|
||||
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.561s
|
||||
Routing Phase 2: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.615s, Elapsed time = 0h 0m 0.616s
|
||||
Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s
|
||||
Total Routing: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 0.766s, Elapsed time = 0h 0m 0.765s
|
||||
CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.734s
|
||||
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 330MB
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 332MB
|
||||
|
||||
|
||||
3. Resource Usage Summary
|
||||
@ -40,15 +40,15 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Resources | Usage | Utilization
|
||||
--------------------------------------------------------------------------------
|
||||
Logic | 954/8640 | 12%
|
||||
--LUT,ALU,ROM16 | 954(700 LUT, 254 ALU, 0 ROM16) | -
|
||||
Logic | 943/8640 | 11%
|
||||
--LUT,ALU,ROM16 | 943(689 LUT, 254 ALU, 0 ROM16) | -
|
||||
--SSRAM(RAM16) | 0 | -
|
||||
Register | 2151/6693 | 33%
|
||||
Register | 2313/6693 | 35%
|
||||
--Logic Register as Latch | 0/6480 | 0%
|
||||
--Logic Register as FF | 2145/6480 | 34%
|
||||
--Logic Register as FF | 2307/6480 | 36%
|
||||
--I/O Register as Latch | 0/213 | 0%
|
||||
--I/O Register as FF | 6/213 | 3%
|
||||
CLS | 1491/4320 | 35%
|
||||
CLS | 1574/4320 | 37%
|
||||
I/O Port | 37/71 | 53%
|
||||
I/O Buf | 31 | -
|
||||
--Input Buf | 8 | -
|
||||
@ -74,8 +74,8 @@
|
||||
------------------------------------------
|
||||
Clock Resource| Usage | Utilization
|
||||
------------------------------------------
|
||||
PRIMARY | 5/8 | 63%
|
||||
LW | 6/8 | 75%
|
||||
PRIMARY | 4/8 | 50%
|
||||
LW | 7/8 | 88%
|
||||
GCLK_PIN | 2/3 | 67%
|
||||
rPLL | 1/2 | 50%
|
||||
==========================================
|
||||
@ -88,15 +88,15 @@
|
||||
-------------------------------------------
|
||||
i2s_in_sclk_d | PRIMARY | TR TL BR BL
|
||||
clock_200M | PRIMARY | TR TL BR BL
|
||||
clock_100M | PRIMARY | TR TL BR BL
|
||||
clock_100M | PRIMARY | TR BR BL
|
||||
main_rx_1_inst/aes3_bclk| PRIMARY | BR
|
||||
main_tx_inst2/serializer/new_data_pos_edge| PRIMARY | TL BL
|
||||
n175_8 | LW | -
|
||||
main_rx_1_inst/demuxer/new_data_re| LW | -
|
||||
main_rx_1_inst/transmitter/n1680_3| LW | -
|
||||
main_tx_inst/deserializer/n1658_4| LW | -
|
||||
main_tx_inst/deserializer/n1844_4| LW | -
|
||||
main_tx_inst/deserializer/sample_ch_1_r_buf_21_6| LW | -
|
||||
main_tx_inst/serializer/new_data_pos_edge| LW | -
|
||||
main_tx_inst2/serializer/new_data_pos_edge| LW | -
|
||||
===========================================
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -41,7 +41,7 @@
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
|
||||
"InstLine" : 58,
|
||||
"InstLine" : 57,
|
||||
"InstName" : "deserializer",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd",
|
||||
"ModuleLine" : 18,
|
||||
@ -49,15 +49,15 @@
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
|
||||
"InstLine" : 83,
|
||||
"InstLine" : 81,
|
||||
"InstName" : "demuxer",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
|
||||
"ModuleLine" : 12,
|
||||
"ModuleLine" : 6,
|
||||
"ModuleName" : "ultranet_rx_demux"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v",
|
||||
"InstLine" : 101,
|
||||
"InstLine" : 98,
|
||||
"InstName" : "transmitter",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_quad_transmitter.vhd",
|
||||
"ModuleLine" : 11,
|
||||
|
||||
@ -52,11 +52,6 @@
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_clocks.vhd",
|
||||
"Type" : "vhdl"
|
||||
},
|
||||
{
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
|
||||
"Type" : "vhdl"
|
||||
},
|
||||
{
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd",
|
||||
@ -71,6 +66,11 @@
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_tx_clocks.vhd",
|
||||
"Type" : "vhdl"
|
||||
},
|
||||
{
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
|
||||
"Type" : "vhdl"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
@ -52,7 +52,6 @@ ultranet_rx_clocks clocks(
|
||||
|
||||
|
||||
wire [23:0] audio_sample;
|
||||
wire [2:0] audio_channel;
|
||||
wire aes3_new_data;
|
||||
|
||||
ultranet_rx_deserializer deserializer(
|
||||
@ -65,7 +64,6 @@ ultranet_rx_deserializer deserializer(
|
||||
.lrclk(aes3_lrck),
|
||||
|
||||
.sample_out(audio_sample),
|
||||
.channel(audio_channel),
|
||||
.new_data(aes3_new_data)
|
||||
);
|
||||
|
||||
@ -84,9 +82,8 @@ ultranet_rx_demux demuxer(
|
||||
.clk(clk),
|
||||
|
||||
.sample_in(audio_sample),
|
||||
.channel(audio_channel),
|
||||
.new_data(aes3_new_data),
|
||||
|
||||
|
||||
.ch1_out(audio_sample_1),
|
||||
.ch2_out(audio_sample_2),
|
||||
.ch3_out(audio_sample_3),
|
||||
|
||||
@ -1,9 +1,3 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Demuxer to split the incomming sound samples into 8 different channels
|
||||
-- Based on
|
||||
-- - https://github.com/xn--nding-jua/UltranetReceiver
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
@ -16,7 +10,7 @@ entity ultranet_rx_demux is
|
||||
|
||||
-- Audio sample and destination channel
|
||||
sample_in : in std_logic_vector(23 downto 0);
|
||||
channel : in unsigned(2 downto 0);
|
||||
--channel : in unsigned(2 downto 0);
|
||||
|
||||
-- Data write signal
|
||||
new_data : in std_logic;
|
||||
@ -34,46 +28,76 @@ entity ultranet_rx_demux is
|
||||
end entity;
|
||||
|
||||
architecture rtl of ultranet_rx_demux is
|
||||
-- New data detector & signal
|
||||
signal znew_data, zznew_data, zzznew_data : std_logic;
|
||||
signal new_data_pos_edge : std_logic;
|
||||
-- Store previous sample and its LSB
|
||||
signal prev_sample : std_logic_vector(23 downto 0);
|
||||
signal prev_lsb : std_logic_vector(1 downto 0);
|
||||
signal curr_lsb : std_logic_vector(1 downto 0);
|
||||
|
||||
-- Edge detector for new_data
|
||||
signal new_data_d : std_logic;
|
||||
signal new_data_re : std_logic; -- rising edge
|
||||
|
||||
-- Double buffering for outputs
|
||||
signal ch1_buf : std_logic_vector(23 downto 0);
|
||||
signal ch2_buf : std_logic_vector(23 downto 0);
|
||||
signal ch3_buf : std_logic_vector(23 downto 0);
|
||||
signal ch4_buf : std_logic_vector(23 downto 0);
|
||||
signal ch5_buf : std_logic_vector(23 downto 0);
|
||||
signal ch6_buf : std_logic_vector(23 downto 0);
|
||||
signal ch7_buf : std_logic_vector(23 downto 0);
|
||||
signal ch8_buf : std_logic_vector(23 downto 0);
|
||||
begin
|
||||
|
||||
detect_edge : process(clk) begin
|
||||
if rising_edge(clk) then
|
||||
znew_data <= new_data;
|
||||
zznew_data <= znew_data;
|
||||
zzznew_data <= zznew_data;
|
||||
if zznew_data = '1' and zzznew_data = '0' then
|
||||
new_data_pos_edge <= '1';
|
||||
else
|
||||
new_data_pos_edge <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
-- Extract current LSB
|
||||
curr_lsb <= sample_in(1 downto 0);
|
||||
|
||||
-- Rising edge detector
|
||||
new_data_re <= new_data and not new_data_d;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- Register new_data for edge detection
|
||||
new_data_d <= new_data;
|
||||
|
||||
if new_data_re = '1' then
|
||||
-- Check if current LSB matches previous LSB
|
||||
if curr_lsb = prev_lsb then
|
||||
-- Two successive samples with same LSB - output them
|
||||
case curr_lsb is
|
||||
when "00" =>
|
||||
ch1_buf <= prev_sample;
|
||||
ch2_buf <= sample_in;
|
||||
when "01" =>
|
||||
ch3_buf <= prev_sample;
|
||||
ch4_buf <= sample_in;
|
||||
when "10" =>
|
||||
ch5_buf <= prev_sample;
|
||||
ch6_buf <= sample_in;
|
||||
when "11" =>
|
||||
ch7_buf <= prev_sample;
|
||||
ch8_buf <= sample_in;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- Store current sample as previous for next comparison
|
||||
prev_sample <= sample_in;
|
||||
prev_lsb <= curr_lsb;
|
||||
|
||||
-- Double buffer - transfer buffer to outputs
|
||||
ch1_out <= ch1_buf(23 downto 2) & "00";
|
||||
ch2_out <= ch2_buf(23 downto 2) & "00";
|
||||
ch3_out <= ch3_buf(23 downto 2) & "00";
|
||||
ch4_out <= ch4_buf(23 downto 2) & "00";
|
||||
ch5_out <= ch5_buf(23 downto 2) & "00";
|
||||
ch6_out <= ch6_buf(23 downto 2) & "00";
|
||||
ch7_out <= ch7_buf(23 downto 2) & "00";
|
||||
ch8_out <= ch8_buf(23 downto 2) & "00";
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk) begin
|
||||
if (rising_edge(clk)) then
|
||||
-- Store individual channels to output-vectors on the rising edge of new data
|
||||
if new_data_pos_edge = '1' then
|
||||
if channel = 0 then
|
||||
ch1_out <= sample_in;
|
||||
elsif channel = 1 then
|
||||
ch2_out <= sample_in;
|
||||
elsif channel = 2 then
|
||||
ch3_out <= sample_in;
|
||||
elsif channel = 3 then
|
||||
ch4_out <= sample_in;
|
||||
elsif channel = 4 then
|
||||
ch5_out <= sample_in;
|
||||
elsif channel = 5 then
|
||||
ch6_out <= sample_in;
|
||||
elsif channel = 6 then
|
||||
ch7_out <= sample_in;
|
||||
elsif channel = 7 then
|
||||
ch8_out <= sample_in;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end rtl;
|
||||
@ -33,9 +33,8 @@ entity ultranet_rx_deserializer is
|
||||
-- Input serial data
|
||||
sdata : in std_logic;
|
||||
|
||||
-- Output sample and destination channel
|
||||
-- Output sample
|
||||
sample_out : out std_logic_vector(23 downto 0);
|
||||
channel : out unsigned(2 downto 0);
|
||||
|
||||
-- New data received signal
|
||||
new_data : out std_logic
|
||||
@ -58,7 +57,6 @@ architecture rtl of ultranet_rx_deserializer is
|
||||
signal in_sound_data_region : std_logic;
|
||||
|
||||
signal bit_counter : integer range 0 to 31 := 0;
|
||||
signal channel_counter : integer range 0 to 7 := 0;
|
||||
|
||||
signal sample_data : std_logic_vector(23 downto 0);
|
||||
begin
|
||||
@ -108,9 +106,8 @@ begin
|
||||
if rising_edge(clk) then
|
||||
-- Check if we are starting a new block
|
||||
if bsync_pos_edge = '1' then
|
||||
-- Yes, reset counters, the channels counter is not set to zero to compensate for processing delays to make sure the demux+transmitter output on the correct channel
|
||||
-- Yes, reset counters
|
||||
bit_counter <= 0;
|
||||
channel_counter <= 4;
|
||||
-- Also reset the new data signal
|
||||
new_data <= '0';
|
||||
else
|
||||
@ -118,12 +115,6 @@ begin
|
||||
if lrclk_edge = '1' then
|
||||
-- Yes, reset the bit counter
|
||||
bit_counter <= 0;
|
||||
-- Increment the channel counter up to the defined number of channels then reset to 0
|
||||
if channel_counter < (CHANNELS-1) then
|
||||
channel_counter <= channel_counter + 1;
|
||||
else
|
||||
channel_counter <= 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Increment the bit counter (up to 32 bits) on a rising edge of the bit clock
|
||||
@ -155,7 +146,6 @@ begin
|
||||
|
||||
-- Send the data out
|
||||
sample_out <= sample_data;
|
||||
channel <= to_unsigned(channel_counter, channel'length);
|
||||
|
||||
get_data : process(clk) begin
|
||||
if rising_edge(clk) then
|
||||
|
||||
@ -22,6 +22,6 @@
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/test_fpga_project_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/test_fpga_project_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd000000020000000000000186000002cafc0200000002fc00000037000002ca0000006200fffffffa000000000200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000037000002ca0000000000000000000000030000078000000150fc0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000000001190000005100fffffffc0000011d00000663000000a100fffffffa000000000100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008c00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100ffffff000005f6000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
|
||||
<Ui>000000ff00000001fd000000020000000000000186000002cafc0200000002fc00000037000001630000000000fffffffa000000000200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000037000002ca0000006200ffffff000000030000078000000150fc0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000000001190000005100fffffffc0000011d00000663000000a100fffffffa000000000100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008c00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100ffffff000005f6000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
|
||||
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|
||||
</UserConfig>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user