Rewrote aes3tx and updaed serialiser
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@ -9,7 +9,7 @@ Analyzing entity 'aes3rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_pr
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3rx.vhd":39)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd'
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Analyzing entity 'aes3tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":11)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":32)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":34)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd'
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Analyzing entity 'i2s_deser'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd":17)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_deser.vhd":35)
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@ -25,19 +25,22 @@ Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\te
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd'
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Analyzing entity 'ultranet_rx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":19)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd":37)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd'
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Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":30)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd'
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Analyzing entity 'ultranet_rx_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":18)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd":44)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd'
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Analyzing entity 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":26)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":28)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd'
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Analyzing entity 'ultranet_tx_clocks'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":6)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd":18)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd'
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Analyzing entity 'ultranet_rx_demux'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":6)
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Analyzing architecture 'rtl'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd":30)
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WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":135)
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Analyzing VHDL file 'C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd'
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Analyzing entity 'aes3tx2'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd":5)
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Analyzing architecture 'behavioral'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd":28)
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WARN (EX3073) : Port 'i2s_in_bclk' remains unconnected for this instance("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":136)
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Compiling module 'top'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":2)
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Compiling module 'gowin_rpll_245'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\gowin_rpll\gowin_rpll_245.v.v":10)
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Compiling module 'main_rx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_rx.v":2)
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@ -64,13 +67,14 @@ Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\H
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Switching to VHDL mode to elaborate design unit 'i2s_quad_deserializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":75)
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Processing 'i2s_quad_deserializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_deserializer.vhd":7)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":75)
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Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":99)
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Switching to VHDL mode to elaborate design unit 'ultranet_serializer'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":103)
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Processing 'ultranet_serializer(rtl)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd":6)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":99)
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Switching to VHDL mode to elaborate design unit 'aes3tx'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":114)
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Processing 'aes3tx(behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":11)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":114)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":103)
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Switching to VHDL mode to elaborate design unit 'aes3tx2'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":118)
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Processing 'aes3tx2(behavioral)'("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd":5)
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Returning to Verilog mode to proceed with elaboration("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":118)
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NOTE (EX0101) : Current top module is "top"
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WARN (EX0211) : The output port "bsync" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":17)
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WARN (EX0211) : The output port "debug_4" of module "main_tx" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main_tx.v":20)
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WARN (EX0211) : The output port "debug_2" of module "top" has no driver, assigning undriven bits to Z, simulation mismatch possible("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":44)
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[5%] Running netlist conversion ...
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@ -81,7 +85,6 @@ WARN (CV0016) : Input ultranet_rx_2 is unused("C:\Projects\In Progress\HyperNet
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WARN (CV0016) : Input key_2 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":40)
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WARN (CV0016) : Input key_3 is unused("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\main.v":41)
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Running device independent optimization ...
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WARN (DI0019) : Merging user defined instance "main_tx_inst2/transmitter/bit_counter[5:0]" to instance "main_tx_inst/transmitter/bit_counter[5:0]", because they are equivalent. If you want to keep the instance, please apply property constraint syn_preserve = 1 on it("C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx.vhd":50)
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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@ -15,10 +15,11 @@
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\i2s_quad_transmitter.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\spdif_transmitter.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_clocks.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_deserializer.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_serializer.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_tx_clocks.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\ultranet_rx_demux.vhd" type="vhdl"/>
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<File path="C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\src\aes3tx2.vhd" type="vhdl"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -63,7 +63,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
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<td align = "center">43</td>
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<td align = "center">5</td>
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<td align = "center">47</td>
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<td align = "center">51</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -93,7 +93,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
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<td align = "center">377</td>
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<td align = "center">-</td>
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<td align = "center">7</td>
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<td align = "center">6</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -103,7 +103,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_rx.v)</td>
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<td align = "center">194</td>
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<td align = "center">-</td>
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<td align = "center">117</td>
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<td align = "center">118</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -121,9 +121,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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</tr>
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<td class="label">        |--clocks
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
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<td align = "center">99</td>
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<td align = "center">93</td>
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<td align = "center">39</td>
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<td align = "center">66</td>
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<td align = "center">62</td>
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<td align = "center">26</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -141,9 +141,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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</tr>
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<td class="label">        |--serializer
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
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<td align = "center">210</td>
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<td align = "center">227</td>
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<td align = "center">-</td>
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<td align = "center">103</td>
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<td align = "center">94</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -152,8 +152,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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<td class="label">        |--transmitter
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
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<td align = "center">130</td>
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<td align = "center">8</td>
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<td align = "center">46</td>
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<td align = "center">13</td>
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<td align = "center">71</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -171,9 +171,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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</tr>
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<td class="label">        |--clocks
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
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<td align = "center">99</td>
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<td align = "center">93</td>
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<td align = "center">39</td>
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<td align = "center">66</td>
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<td align = "center">62</td>
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<td align = "center">26</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -191,9 +191,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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</tr>
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<td class="label">        |--serializer
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
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<td align = "center">210</td>
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<td align = "center">227</td>
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<td align = "center">-</td>
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<td align = "center">103</td>
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<td align = "center">94</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -201,9 +201,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
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</tr>
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<td class="label">        |--transmitter
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(C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v)</td>
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<td align = "center">91</td>
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<td align = "center">129</td>
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<td align = "center">13</td>
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<td align = "center">43</td>
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<td align = "center">70</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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@ -1,23 +1,23 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<Module name="top" Lut="2" T_Register="2313(0)" T_Alu="243(0)" T_Lut="695(2)">
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<Module name="top" Lut="2" T_Register="2319(0)" T_Alu="186(0)" T_Lut="707(2)">
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<SubModule name="pll_main_clock"/>
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<SubModule name="main_rx_1_inst" T_Register="730(0)" T_Alu="36(0)" T_Lut="272(0)">
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<SubModule name="receiver" Register="43" Alu="5" Lut="47" T_Register="43(43)" T_Alu="5(5)" T_Lut="47(47)"/>
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<SubModule name="main_rx_1_inst" T_Register="730(0)" T_Alu="36(0)" T_Lut="276(0)">
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<SubModule name="receiver" Register="43" Alu="5" Lut="51" T_Register="43(43)" T_Alu="5(5)" T_Lut="51(51)"/>
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<SubModule name="clocks" Register="78" Alu="31" Lut="81" T_Register="78(78)" T_Alu="31(31)" T_Lut="81(81)"/>
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<SubModule name="deserializer" Register="38" Lut="20" T_Register="38(38)" T_Lut="20(20)"/>
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<SubModule name="demuxer" Register="377" Lut="7" T_Register="377(377)" T_Lut="7(7)"/>
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<SubModule name="transmitter" Register="194" Lut="117" T_Register="194(194)" T_Lut="117(117)"/>
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<SubModule name="demuxer" Register="377" Lut="6" T_Register="377(377)" T_Lut="6(6)"/>
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<SubModule name="transmitter" Register="194" Lut="118" T_Register="194(194)" T_Lut="118(118)"/>
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</SubModule>
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<SubModule name="main_tx_inst" T_Register="813(0)" T_Alu="101(0)" T_Lut="213(0)">
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<SubModule name="clocks" Register="99" Alu="93" Lut="39" T_Register="99(99)" T_Alu="93(93)" T_Lut="39(39)"/>
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<SubModule name="main_tx_inst" T_Register="797(0)" T_Alu="75(0)" T_Lut="216(0)">
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<SubModule name="clocks" Register="66" Alu="62" Lut="26" T_Register="66(66)" T_Alu="62(62)" T_Lut="26(26)"/>
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<SubModule name="deserializer" Register="374" Lut="25" T_Register="374(374)" T_Lut="25(25)"/>
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<SubModule name="serializer" Register="210" Lut="103" T_Register="210(210)" T_Lut="103(103)"/>
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<SubModule name="transmitter" Register="130" Alu="8" Lut="46" T_Register="130(130)" T_Alu="8(8)" T_Lut="46(46)"/>
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<SubModule name="serializer" Register="227" Lut="94" T_Register="227(227)" T_Lut="94(94)"/>
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<SubModule name="transmitter" Register="130" Alu="13" Lut="71" T_Register="130(130)" T_Alu="13(13)" T_Lut="71(71)"/>
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</SubModule>
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<SubModule name="main_tx_inst2" T_Register="770(0)" T_Alu="106(0)" T_Lut="208(0)">
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<SubModule name="clocks" Register="99" Alu="93" Lut="39" T_Register="99(99)" T_Alu="93(93)" T_Lut="39(39)"/>
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<SubModule name="main_tx_inst2" T_Register="792(0)" T_Alu="75(0)" T_Lut="213(0)">
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<SubModule name="clocks" Register="66" Alu="62" Lut="26" T_Register="66(66)" T_Alu="62(62)" T_Lut="26(26)"/>
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<SubModule name="deserializer" Register="370" Lut="23" T_Register="370(370)" T_Lut="23(23)"/>
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<SubModule name="serializer" Register="210" Lut="103" T_Register="210(210)" T_Lut="103(103)"/>
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<SubModule name="transmitter" Register="91" Alu="13" Lut="43" T_Register="91(91)" T_Alu="13(13)" T_Lut="43(43)"/>
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<SubModule name="serializer" Register="227" Lut="94" T_Register="227(227)" T_Lut="94(94)"/>
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<SubModule name="transmitter" Register="129" Alu="13" Lut="70" T_Register="129(129)" T_Alu="13(13)" T_Lut="70(70)"/>
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</SubModule>
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</Module>
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||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -28,5 +28,5 @@ Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\p
|
||||
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.html" completed
|
||||
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.rpt.txt" completed
|
||||
Generate file "C:\Projects\In Progress\HyperNet\src\hdl\test_fpga_project\impl\pnr\test_fpga_project.tr.html" completed
|
||||
Sat Oct 4 16:56:29 2025
|
||||
Sat Oct 4 23:28:28 2025
|
||||
|
||||
|
||||
@ -78,7 +78,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Oct 4 16:56:29 2025
|
||||
<td>Sat Oct 4 23:28:28 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
||||
@ -89,7 +89,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Oct 4 16:56:29 2025
|
||||
<td>Sat Oct 4 23:28:28 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -161,7 +161,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Total Power (mW)</td>
|
||||
<td>37.498</td>
|
||||
<td>35.826</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Quiescent Power (mW)</td>
|
||||
@ -169,7 +169,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Dynamic Power (mW)</td>
|
||||
<td>10.963</td>
|
||||
<td>9.291</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Psram Power (mW)</td>
|
||||
@ -180,7 +180,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Junction Temperature</td>
|
||||
<td>25.770</td>
|
||||
<td>25.735</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Theta JA</td>
|
||||
@ -188,7 +188,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Max Allowed Ambient Temperature</td>
|
||||
<td>84.230</td>
|
||||
<td>84.265</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Supply_Summary">Supply Information:</a></h2>
|
||||
@ -203,30 +203,30 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<tr>
|
||||
<td>VCC</td>
|
||||
<td>1.200</td>
|
||||
<td>6.930</td>
|
||||
<td>6.326</td>
|
||||
<td>3.507</td>
|
||||
<td>12.525</td>
|
||||
<td>11.801</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCX</td>
|
||||
<td>3.300</td>
|
||||
<td>0.411</td>
|
||||
<td>0.265</td>
|
||||
<td>5.000</td>
|
||||
<td>17.855</td>
|
||||
<td>17.373</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCIO18</td>
|
||||
<td>1.800</td>
|
||||
<td>0.041</td>
|
||||
<td>0.031</td>
|
||||
<td>0.565</td>
|
||||
<td>1.092</td>
|
||||
<td>1.073</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCIO33</td>
|
||||
<td>3.300</td>
|
||||
<td>0.369</td>
|
||||
<td>0.234</td>
|
||||
<td>1.457</td>
|
||||
<td>6.027</td>
|
||||
<td>5.580</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Power Details</a></h1>
|
||||
@ -240,15 +240,15 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Logic</td>
|
||||
<td>0.940</td>
|
||||
<td>0.410</td>
|
||||
<td>NA</td>
|
||||
<td>17.770</td>
|
||||
<td>6.682</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>IO</td>
|
||||
<td>10.166
|
||||
<td>9.042
|
||||
<td>7.026
|
||||
<td>11.304
|
||||
<td>6.250
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PLL</td>
|
||||
@ -266,16 +266,16 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td>top</td>
|
||||
<td>7.795</td>
|
||||
<td>7.795(7.795)</td>
|
||||
<td>7.265</td>
|
||||
<td>7.265(7.265)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/</td>
|
||||
<td>0.250</td>
|
||||
<td>0.250(0.250)</td>
|
||||
<td>0.252</td>
|
||||
<td>0.252(0.252)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/clocks/</td>
|
||||
<td>0.064</td>
|
||||
<td>0.064(0.000)</td>
|
||||
<td>0.065</td>
|
||||
<td>0.065(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/demuxer/</td>
|
||||
<td>0.067</td>
|
||||
@ -286,52 +286,52 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<td>0.013(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/receiver/</td>
|
||||
<td>0.036</td>
|
||||
<td>0.036(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/transmitter/</td>
|
||||
<td>0.072</td>
|
||||
<td>0.072(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/</td>
|
||||
<td>0.079</td>
|
||||
<td>0.079(0.079)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/clocks/</td>
|
||||
<td>0.035</td>
|
||||
<td>0.035(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_rx_1_inst/transmitter/</td>
|
||||
<td>0.071</td>
|
||||
<td>0.071(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/</td>
|
||||
<td>0.345</td>
|
||||
<td>0.345(0.345)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/clocks/</td>
|
||||
<td>0.053</td>
|
||||
<td>0.053(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/deserializer/</td>
|
||||
<td>0.143</td>
|
||||
<td>0.143(0.000)</td>
|
||||
<td>0.014</td>
|
||||
<td>0.014(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/serializer/</td>
|
||||
<td>0.138</td>
|
||||
<td>0.138(0.000)</td>
|
||||
<td>0.014</td>
|
||||
<td>0.014(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst/transmitter/</td>
|
||||
<td>0.011</td>
|
||||
<td>0.011(0.000)</td>
|
||||
<td>0.015</td>
|
||||
<td>0.015(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst2/</td>
|
||||
<td>0.344</td>
|
||||
<td>0.344(0.344)</td>
|
||||
<td>0.079</td>
|
||||
<td>0.079(0.079)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst2/clocks/</td>
|
||||
<td>0.053</td>
|
||||
<td>0.053(0.000)</td>
|
||||
<td>0.035</td>
|
||||
<td>0.035(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst2/deserializer/</td>
|
||||
<td>0.141</td>
|
||||
<td>0.141(0.000)</td>
|
||||
<td>0.014</td>
|
||||
<td>0.014(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst2/serializer/</td>
|
||||
<td>0.138</td>
|
||||
<td>0.138(0.000)</td>
|
||||
<td>0.014</td>
|
||||
<td>0.014(0.000)</td>
|
||||
<tr>
|
||||
<td>top/main_tx_inst2/transmitter/</td>
|
||||
<td>0.012</td>
|
||||
<td>0.012(0.000)</td>
|
||||
<td>0.015</td>
|
||||
<td>0.015(0.000)</td>
|
||||
<tr>
|
||||
<td>top/pll_main_clock/</td>
|
||||
<td>6.855</td>
|
||||
@ -345,30 +345,25 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<th class="label">Total Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NO CLOCK DOMAIN</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>i2s_in_sclk</td>
|
||||
<td>24.576</td>
|
||||
<td>6.987</td>
|
||||
<td>7.015</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>pll_main_clock/rpll_inst/CLKOUTD.default_gen_clk</td>
|
||||
<td>122.880</td>
|
||||
<td>0.220</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>pll_main_clock/rpll_inst/CLKOUT.default_gen_clk</td>
|
||||
<td>245.760</td>
|
||||
<td>0.577</td>
|
||||
<td>0.222</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>main_rx_1_inst/aes3_bclk</td>
|
||||
<td>50.000</td>
|
||||
<td>0.038</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NO CLOCK DOMAIN</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
|
||||
@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Oct 4 16:56:29 2025
|
||||
<td>Sat Oct 4 23:28:28 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -97,24 +97,24 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<tr>
|
||||
<td class="label">Place & Route Process</td>
|
||||
<td>Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.204s, Elapsed time = 0h 0m 0.204s
|
||||
Placement Phase 0: CPU time = 0h 0m 0.183s, Elapsed time = 0h 0m 0.183s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.091s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.741s, Elapsed time = 0h 0m 0.741s
|
||||
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.715s, Elapsed time = 0h 0m 0.715s
|
||||
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
|
||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.615s, Elapsed time = 0h 0m 0.616s
|
||||
Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
|
||||
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.002s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.608s, Elapsed time = 0h 0m 0.608s
|
||||
Routing Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
|
||||
Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.734s
|
||||
CPU time = 0h 0m 0.743s, Elapsed time = 0h 0m 0.742s
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 332MB</td>
|
||||
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 336MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<br/>
|
||||
@ -129,12 +129,12 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>943/8640</td>
|
||||
<td>897/8640</td>
|
||||
<td>11%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --LUT,ALU,ROM16</td>
|
||||
<td>943(689 LUT, 254 ALU, 0 ROM16)</td>
|
||||
<td>897(701 LUT, 196 ALU, 0 ROM16)</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -144,7 +144,7 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>2313/6693</td>
|
||||
<td>2319/6693</td>
|
||||
<td>35%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -154,7 +154,7 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --Logic Register as FF</td>
|
||||
<td>2307/6480</td>
|
||||
<td>2314/6480</td>
|
||||
<td>36%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -164,13 +164,13 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --I/O Register as FF</td>
|
||||
<td>6/213</td>
|
||||
<td>5/213</td>
|
||||
<td>3%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">CLS</td>
|
||||
<td>1574/4320</td>
|
||||
<td>37%</td>
|
||||
<td>1537/4320</td>
|
||||
<td>36%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">I/O Port</td>
|
||||
@ -232,8 +232,8 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">LW</td>
|
||||
<td>7/8</td>
|
||||
<td>88%</td>
|
||||
<td>8/8</td>
|
||||
<td>100%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GCLK_PIN</td>
|
||||
@ -260,11 +260,6 @@ Generate output files:
|
||||
<td> TR TL BR BL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">clock_200M</td>
|
||||
<td>PRIMARY</td>
|
||||
<td> TR TL BR BL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">clock_100M</td>
|
||||
<td>PRIMARY</td>
|
||||
<td> TR BR BL</td>
|
||||
@ -275,9 +270,9 @@ Generate output files:
|
||||
<td> BR</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">n175_8</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
<td class="label">main_tx_inst2/transmitter/n195_7</td>
|
||||
<td>PRIMARY</td>
|
||||
<td> TL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_rx_1_inst/demuxer/new_data_re</td>
|
||||
@ -295,7 +290,7 @@ Generate output files:
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst/deserializer/n1844_4</td>
|
||||
<td class="label">main_tx_inst/deserializer/n2035_3</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
@ -305,6 +300,16 @@ Generate output files:
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst/transmitter/n195_7</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst2/deserializer/n1658_4</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">main_tx_inst2/serializer/new_data_pos_edge</td>
|
||||
<td>LW</td>
|
||||
<td> -</td>
|
||||
|
||||
@ -12,27 +12,27 @@
|
||||
<Part Number>: GW1NR-LV9QN88PC6/I5
|
||||
<Device>: GW1NR-9
|
||||
<Device Version>: C
|
||||
<Created Time>:Sat Oct 4 16:56:29 2025
|
||||
<Created Time>:Sat Oct 4 23:28:28 2025
|
||||
|
||||
|
||||
2. PnR Details
|
||||
|
||||
Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.204s, Elapsed time = 0h 0m 0.204s
|
||||
Placement Phase 0: CPU time = 0h 0m 0.183s, Elapsed time = 0h 0m 0.183s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.091s, Elapsed time = 0h 0m 0.091s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.741s, Elapsed time = 0h 0m 0.741s
|
||||
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.715s, Elapsed time = 0h 0m 0.715s
|
||||
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
|
||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.615s, Elapsed time = 0h 0m 0.616s
|
||||
Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
|
||||
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.002s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.608s, Elapsed time = 0h 0m 0.608s
|
||||
Routing Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
|
||||
Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.734s
|
||||
CPU time = 0h 0m 0.743s, Elapsed time = 0h 0m 0.742s
|
||||
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 332MB
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 336MB
|
||||
|
||||
|
||||
3. Resource Usage Summary
|
||||
@ -40,15 +40,15 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Resources | Usage | Utilization
|
||||
--------------------------------------------------------------------------------
|
||||
Logic | 943/8640 | 11%
|
||||
--LUT,ALU,ROM16 | 943(689 LUT, 254 ALU, 0 ROM16) | -
|
||||
Logic | 897/8640 | 11%
|
||||
--LUT,ALU,ROM16 | 897(701 LUT, 196 ALU, 0 ROM16) | -
|
||||
--SSRAM(RAM16) | 0 | -
|
||||
Register | 2313/6693 | 35%
|
||||
Register | 2319/6693 | 35%
|
||||
--Logic Register as Latch | 0/6480 | 0%
|
||||
--Logic Register as FF | 2307/6480 | 36%
|
||||
--Logic Register as FF | 2314/6480 | 36%
|
||||
--I/O Register as Latch | 0/213 | 0%
|
||||
--I/O Register as FF | 6/213 | 3%
|
||||
CLS | 1574/4320 | 37%
|
||||
--I/O Register as FF | 5/213 | 3%
|
||||
CLS | 1537/4320 | 36%
|
||||
I/O Port | 37/71 | 53%
|
||||
I/O Buf | 31 | -
|
||||
--Input Buf | 8 | -
|
||||
@ -75,7 +75,7 @@
|
||||
Clock Resource| Usage | Utilization
|
||||
------------------------------------------
|
||||
PRIMARY | 4/8 | 50%
|
||||
LW | 7/8 | 88%
|
||||
LW | 8/8 | 100%
|
||||
GCLK_PIN | 2/3 | 67%
|
||||
rPLL | 1/2 | 50%
|
||||
==========================================
|
||||
@ -87,15 +87,16 @@
|
||||
Signal | Global Clock | Location
|
||||
-------------------------------------------
|
||||
i2s_in_sclk_d | PRIMARY | TR TL BR BL
|
||||
clock_200M | PRIMARY | TR TL BR BL
|
||||
clock_100M | PRIMARY | TR BR BL
|
||||
main_rx_1_inst/aes3_bclk| PRIMARY | BR
|
||||
n175_8 | LW | -
|
||||
main_tx_inst2/transmitter/n195_7| PRIMARY | TL
|
||||
main_rx_1_inst/demuxer/new_data_re| LW | -
|
||||
main_rx_1_inst/transmitter/n1680_3| LW | -
|
||||
main_tx_inst/deserializer/n1658_4| LW | -
|
||||
main_tx_inst/deserializer/n1844_4| LW | -
|
||||
main_tx_inst/deserializer/n2035_3| LW | -
|
||||
main_tx_inst/serializer/new_data_pos_edge| LW | -
|
||||
main_tx_inst/transmitter/n195_7| LW | -
|
||||
main_tx_inst2/deserializer/n1658_4| LW | -
|
||||
main_tx_inst2/serializer/new_data_pos_edge| LW | -
|
||||
===========================================
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -48,7 +48,7 @@ function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.
|
||||
</li>
|
||||
<!--Setup_Slack_Table end-->
|
||||
<!--Hold_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="test_fpga_project_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;color: #FF0000;" class = "error" target="mainFrame">Hold Paths Table</a>
|
||||
<li><div class="triangle_fake"></div><a href="test_fpga_project_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
|
||||
</li>
|
||||
<!--Hold_Slack_Table end-->
|
||||
<!--Recovery_Slack_Table begin-->
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -91,7 +91,7 @@
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
|
||||
"InstLine" : 82,
|
||||
"InstLine" : 84,
|
||||
"InstName" : "serializer",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_serializer.vhd",
|
||||
"ModuleLine" : 6,
|
||||
@ -99,11 +99,11 @@
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
|
||||
"InstLine" : 102,
|
||||
"InstLine" : 105,
|
||||
"InstName" : "transmitter",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
|
||||
"ModuleLine" : 11,
|
||||
"ModuleName" : "aes3tx"
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx2.vhd",
|
||||
"ModuleLine" : 5,
|
||||
"ModuleName" : "aes3tx2"
|
||||
}
|
||||
]
|
||||
},
|
||||
@ -133,7 +133,7 @@
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
|
||||
"InstLine" : 82,
|
||||
"InstLine" : 84,
|
||||
"InstName" : "serializer",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_serializer.vhd",
|
||||
"ModuleLine" : 6,
|
||||
@ -141,16 +141,24 @@
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/main_tx.v",
|
||||
"InstLine" : 102,
|
||||
"InstLine" : 105,
|
||||
"InstName" : "transmitter",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
|
||||
"ModuleLine" : 11,
|
||||
"ModuleName" : "aes3tx"
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx2.vhd",
|
||||
"ModuleLine" : 5,
|
||||
"ModuleName" : "aes3tx2"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
|
||||
"InstLine" : 11,
|
||||
"InstName" : "aes3tx",
|
||||
"ModuleFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx.vhd",
|
||||
"ModuleLine" : 11,
|
||||
"ModuleName" : "aes3tx"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/i2s_deser.vhd",
|
||||
"InstLine" : 17,
|
||||
|
||||
@ -52,6 +52,11 @@
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_clocks.vhd",
|
||||
"Type" : "vhdl"
|
||||
},
|
||||
{
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
|
||||
"Type" : "vhdl"
|
||||
},
|
||||
{
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_deserializer.vhd",
|
||||
@ -69,7 +74,7 @@
|
||||
},
|
||||
{
|
||||
"Library" : "work",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/ultranet_rx_demux.vhd",
|
||||
"Path" : "C:/Projects/In Progress/HyperNet/src/hdl/test_fpga_project/src/aes3tx2.vhd",
|
||||
"Type" : "vhdl"
|
||||
}
|
||||
],
|
||||
|
||||
@ -17,6 +17,8 @@ entity aes3tx is
|
||||
);
|
||||
port
|
||||
(
|
||||
reset_n : in std_logic;
|
||||
|
||||
bit_clock : in std_logic; -- 128x Fsample (6.144MHz for 48K samplerate)
|
||||
sample : in std_logic_vector(23 downto 0);
|
||||
biphase_out : out std_logic;
|
||||
@ -45,7 +47,9 @@ begin
|
||||
|
||||
bit_clock_counter : process (bit_clock)
|
||||
begin
|
||||
if bit_clock'event and bit_clock = '1' then
|
||||
if reset_n = '0' then
|
||||
bit_counter <= (others => '0');
|
||||
elsif bit_clock'event and bit_clock = '1' then
|
||||
bit_counter <= bit_counter + 1;
|
||||
end if;
|
||||
end process bit_clock_counter;
|
||||
@ -140,7 +144,9 @@ begin
|
||||
|
||||
biphaser : process (bit_clock)
|
||||
begin
|
||||
if bit_clock'event and bit_clock = '1' then
|
||||
if reset_n = '0' then
|
||||
data_biphase <= '0';
|
||||
elsif bit_clock'event and bit_clock = '1' then
|
||||
if data_out_buffer(data_out_buffer'left) = '1' then
|
||||
data_biphase <= not data_biphase;
|
||||
end if;
|
||||
|
||||
163
src/hdl/test_fpga_project/src/aes3tx2.vhd
Normal file
163
src/hdl/test_fpga_project/src/aes3tx2.vhd
Normal file
@ -0,0 +1,163 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity aes3tx2 is
|
||||
generic(
|
||||
FRAME_COUNTER_LAST : std_logic_vector(8 downto 0) := "101111111";
|
||||
AES3_PREAMBLE_X : std_logic_vector(7 downto 0) := "10010011";
|
||||
AES3_PREAMBLE_Y : std_logic_vector(7 downto 0) := "10010110";
|
||||
AES3_PREAMBLE_Z : std_logic_vector(7 downto 0) := "10011100"
|
||||
);
|
||||
port (
|
||||
reset_n : in std_logic; -- Active low reset
|
||||
clk : in std_logic; -- Bit clock (e.g., 128*Fs for 48kHz = 6.144 MHz)
|
||||
|
||||
load : out std_logic; -- Request new audio samples
|
||||
left_data : in std_logic_vector(23 downto 0); -- 24-bit left channel
|
||||
right_data : in std_logic_vector(23 downto 0); -- 24-bit right channel
|
||||
|
||||
valid : in std_logic;
|
||||
channel_status : in std_logic_vector(383 downto 0);
|
||||
user_status : in std_logic_vector(383 downto 0);
|
||||
|
||||
aes3_out : inout std_logic -- AES3 serial output
|
||||
);
|
||||
end aes3tx2;
|
||||
|
||||
architecture behavioral of aes3tx2 is
|
||||
signal sample_buf : std_logic_vector(23 downto 0);
|
||||
|
||||
signal bit_counter : std_logic_vector(5 downto 0) := (others => '0');
|
||||
signal frame_counter : std_logic_vector(8 downto 0) := (others => '0');
|
||||
signal data_out_buffer : std_logic_vector(7 downto 0);
|
||||
|
||||
signal parity : std_logic;
|
||||
signal channel_status_shift : std_logic_vector(383 downto 0);
|
||||
signal user_status_shift : std_logic_vector(383 downto 0);
|
||||
|
||||
signal channel_r : std_logic := '0';
|
||||
|
||||
signal data_biphase : std_logic := '0';
|
||||
|
||||
begin
|
||||
bit_clock_counter : process (clk) begin
|
||||
if rising_edge(clk) then
|
||||
if reset_n = '0' then
|
||||
bit_counter <= (others => '0');
|
||||
else
|
||||
bit_counter <= bit_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process bit_clock_counter;
|
||||
|
||||
data_latch : process (clk) begin
|
||||
if rising_edge(clk) then
|
||||
parity <= valid xor user_status_shift(383) xor channel_status_shift(383) xor sample_buf(23) xor sample_buf(22) xor sample_buf(21) xor sample_buf(20) xor sample_buf(19) xor sample_buf(18) xor sample_buf(17) xor sample_buf(16) xor sample_buf(15) xor sample_buf(14) xor sample_buf(13) xor sample_buf(12) xor sample_buf(11) xor sample_buf(10) xor sample_buf(9) xor sample_buf(8) xor sample_buf(7) xor sample_buf(6) xor sample_buf(5) xor sample_buf(4) xor sample_buf(3) xor sample_buf(2) xor sample_buf(1) xor sample_buf(0);
|
||||
|
||||
if bit_counter = 2 and channel_r = '0' then
|
||||
load <= '1';
|
||||
else
|
||||
load <= '0';
|
||||
end if;
|
||||
|
||||
if bit_counter = 6 then -- We are near the end of the preamble, load the sound data in the buffer
|
||||
if channel_r = '0' then
|
||||
sample_buf <= left_data;
|
||||
else
|
||||
sample_buf <= right_data;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if bit_counter = 63 then
|
||||
-- We are at the 32th bit (2x due to biphase) which means the end of a frame
|
||||
|
||||
-- Check if this is the last frame in the audio block
|
||||
if frame_counter = FRAME_COUNTER_LAST then
|
||||
-- Yes, reset the frame counter
|
||||
frame_counter <= (others => '0');
|
||||
else
|
||||
-- Nope, increment the frame counter
|
||||
frame_counter <= frame_counter + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process data_latch;
|
||||
|
||||
|
||||
data_output : process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if bit_counter = 63 then
|
||||
-- We are at the 32th bit of the frame (2x due to biphase) which means the end of a frame
|
||||
|
||||
-- Check if this is the last frame in the audio block
|
||||
if frame_counter = FRAME_COUNTER_LAST then
|
||||
-- Next frame will be the first of the new audio block, load the Z preamble
|
||||
data_out_buffer <= AES3_PREAMBLE_Z;
|
||||
channel_status_shift <= channel_status;
|
||||
user_status_shift <= user_status;
|
||||
channel_r <= '0';
|
||||
else
|
||||
-- Next frame is NOT the first of the audio block
|
||||
-- Check if the frame is even/odd (generally attributed to left/right)
|
||||
if frame_counter(0) = '1' then
|
||||
-- Next frame is even, load the X preamble
|
||||
data_out_buffer <= AES3_PREAMBLE_X ;
|
||||
channel_r <= '0';
|
||||
else
|
||||
-- Next frame is odd, load the Y preamble
|
||||
data_out_buffer <= AES3_PREAMBLE_Y;
|
||||
channel_r <= '1';
|
||||
end if;
|
||||
-- Shift the channel status and user by one to the left
|
||||
channel_status_shift <= channel_status_shift(382 downto 0) & '0';
|
||||
user_status_shift <= user_status_shift(382 downto 0) & '0';
|
||||
end if;
|
||||
else
|
||||
|
||||
|
||||
if bit_counter(2 downto 0) = "111" then -- load new part of data into buffer
|
||||
case bit_counter(5 downto 3) is
|
||||
when "000" =>
|
||||
data_out_buffer <= '1' & sample_buf(0) & '1' & sample_buf(1) & '1' & sample_buf(2) & '1' & sample_buf(3);
|
||||
when "001" =>
|
||||
data_out_buffer <= '1' & sample_buf(4) & '1' & sample_buf(5) & '1' & sample_buf(6) & '1' & sample_buf(7);
|
||||
when "010" =>
|
||||
data_out_buffer <= '1' & sample_buf(8) & '1' & sample_buf(9) & '1' & sample_buf(10) & '1' & sample_buf(11);
|
||||
when "011" =>
|
||||
data_out_buffer <= '1' & sample_buf(12) & '1' & sample_buf(13) & '1' & sample_buf(14) & '1' & sample_buf(15);
|
||||
when "100" =>
|
||||
data_out_buffer <= '1' & sample_buf(16) & '1' & sample_buf(17) & '1' & sample_buf(18) & '1' & sample_buf(19);
|
||||
when "101" =>
|
||||
data_out_buffer <= '1' & sample_buf(20) & '1' & sample_buf(21) & '1' & sample_buf(22) & '1' & sample_buf(23);
|
||||
when "110" =>
|
||||
data_out_buffer <= "1" & valid & "1" & user_status_shift(383) & "1" & channel_status_shift(383) & "1" & parity;
|
||||
when others =>
|
||||
end case;
|
||||
else
|
||||
data_out_buffer <= data_out_buffer(6 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process data_output;
|
||||
|
||||
|
||||
biphaser : process (clk) begin
|
||||
if rising_edge(clk) then
|
||||
if reset_n = '0' then
|
||||
data_biphase <= '0';
|
||||
else
|
||||
if data_out_buffer(data_out_buffer'left) = '1' then
|
||||
data_biphase <= not data_biphase;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process biphaser;
|
||||
|
||||
aes3_out <= data_biphase;
|
||||
|
||||
end behavioral;
|
||||
@ -105,6 +105,7 @@ main_tx main_tx_inst(
|
||||
.aes3_tx(ultranet_tx_1),
|
||||
|
||||
.channel_status(384'b000000000000000000000000000000000000000000000000000000000000000011000000111100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
//.channel_status(384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
.user_status (384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
.valid(1'b1),
|
||||
|
||||
@ -113,7 +114,6 @@ main_tx main_tx_inst(
|
||||
.bsync(debug_1)
|
||||
);
|
||||
|
||||
|
||||
assign led_ultranet_tx2 = 0;
|
||||
main_tx main_tx_inst2(
|
||||
.clk(clock_200M),
|
||||
@ -129,7 +129,8 @@ main_tx main_tx_inst2(
|
||||
|
||||
.aes3_tx(ultranet_tx_2),
|
||||
|
||||
.channel_status(384'b000000000000000000000000000000001100000011110011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
.channel_status(384'b000000000000000000000000000000000000000000000000000000000000000011000000111100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
//.channel_status(384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
.user_status (384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
|
||||
.valid(1'b1)
|
||||
);
|
||||
|
||||
@ -51,7 +51,7 @@ wire [23:0] audio_sample_8;
|
||||
wire i2s_new_data;
|
||||
|
||||
i2s_quad_deserializer deserializer(
|
||||
.clk(clk),
|
||||
.clk(aes_bclk),
|
||||
.bsync(!reset_n),
|
||||
|
||||
.bclk(i2s_in_bclk),
|
||||
@ -76,11 +76,13 @@ i2s_quad_deserializer deserializer(
|
||||
|
||||
assign debug_3 = i2s_new_data;
|
||||
|
||||
wire [23:0] i2s_sample;
|
||||
wire [23:0] i2s_samplel;
|
||||
wire [23:0] i2s_sampler;
|
||||
wire load;
|
||||
|
||||
|
||||
ultranet_serializer serializer(
|
||||
.clk(clk),
|
||||
.clk(aes_bclk),
|
||||
|
||||
.new_data(i2s_new_data),
|
||||
|
||||
@ -95,22 +97,24 @@ ultranet_serializer serializer(
|
||||
.ch7_in(audio_sample_7),
|
||||
.ch8_in(audio_sample_8),
|
||||
|
||||
.ch_out(i2s_sample)
|
||||
.load(load),
|
||||
.ch_out_l(i2s_samplel),
|
||||
.ch_out_r(i2s_sampler)
|
||||
);
|
||||
|
||||
aes3tx2 transmitter(
|
||||
.reset_n(reset_n),
|
||||
.clk(aes_bclk),
|
||||
|
||||
aes3tx transmitter(
|
||||
.bit_clock(aes_bclk),
|
||||
|
||||
.sample(i2s_sample),
|
||||
.load(load),
|
||||
.left_data(i2s_samplel),
|
||||
.right_data(i2s_sampler),
|
||||
|
||||
.user_status(user_status),
|
||||
.channel_status(channel_status),
|
||||
.valid(valid),
|
||||
|
||||
.bsync(bsync),
|
||||
|
||||
.biphase_out(aes3_tx)
|
||||
.aes3_out(aes3_tx)
|
||||
);
|
||||
|
||||
|
||||
|
||||
@ -19,7 +19,9 @@ entity ultranet_serializer is
|
||||
aes_lrck : in std_logic;
|
||||
|
||||
|
||||
ch_out : out std_logic_vector(23 downto 0)
|
||||
load : in std_logic;
|
||||
ch_out_l : out std_logic_vector(23 downto 0);
|
||||
ch_out_r : out std_logic_vector(23 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
@ -27,6 +29,8 @@ architecture rtl of ultranet_serializer is
|
||||
signal new_data_pos_edge : std_logic;
|
||||
signal znew_data : std_logic;
|
||||
signal aes_lrck_edge : std_logic;
|
||||
signal aes_lrck_neg_edge : std_logic;
|
||||
signal aes_lrck_pos_edge : std_logic;
|
||||
signal zaes_lrck : std_logic;
|
||||
signal zzaes_lrck : std_logic;
|
||||
signal zzzaes_lrck : std_logic;
|
||||
@ -40,7 +44,7 @@ architecture rtl of ultranet_serializer is
|
||||
signal ch7_buffer : std_logic_vector(23 downto 0);
|
||||
signal ch8_buffer : std_logic_vector(23 downto 0);
|
||||
|
||||
signal channel_cnt : integer range 0 to 7 := 0; -- TODO: range should be 0 to 7 for the 8 ADCs
|
||||
signal channel_cnt : integer range 0 to 3 := 0;
|
||||
begin
|
||||
detect_new_data_edge : process(clk) begin
|
||||
if rising_edge(clk) then
|
||||
@ -58,9 +62,15 @@ begin
|
||||
zaes_lrck <= aes_lrck;
|
||||
zzaes_lrck <= zaes_lrck;
|
||||
zzzaes_lrck <= zzaes_lrck;
|
||||
if zzaes_lrck /= zzzaes_lrck then
|
||||
if zzaes_lrck = '1' and zzzaes_lrck = '0' then
|
||||
aes_lrck_pos_edge <= '1';
|
||||
aes_lrck_edge <= '1';
|
||||
elsif zzaes_lrck = '0' and zzzaes_lrck = '1' then
|
||||
aes_lrck_neg_edge <= '1';
|
||||
aes_lrck_edge <= '1';
|
||||
else
|
||||
aes_lrck_pos_edge <= '0';
|
||||
aes_lrck_neg_edge <= '0';
|
||||
aes_lrck_edge <= '0';
|
||||
end if;
|
||||
end if;
|
||||
@ -80,33 +90,31 @@ begin
|
||||
ch7_buffer <= ch7_in;
|
||||
ch8_buffer <= ch8_in;
|
||||
|
||||
|
||||
-- Reset the channel counter to the last channel, this is unusual but the
|
||||
-- aes_lrck_edge comming a short time after the new_data will overflow the counter to the
|
||||
-- first channel
|
||||
channel_cnt <= 0; -- TODO: reset value should be 7 for 8 ADCs
|
||||
channel_cnt <= 0;
|
||||
end if;
|
||||
|
||||
if aes_lrck_edge = '1' then
|
||||
if load = '1' then
|
||||
-- Increment the channel counter on each pulse
|
||||
channel_cnt <= channel_cnt + 1;
|
||||
|
||||
channel_cnt <= channel_cnt + 1;
|
||||
|
||||
-- Output the corrsponding sample
|
||||
if channel_cnt = 0 then
|
||||
ch_out <= ch1_buffer;
|
||||
ch_out_l <= ch1_buffer;
|
||||
ch_out_r <= ch2_buffer;
|
||||
elsif channel_cnt = 1 then
|
||||
ch_out <= ch2_buffer;
|
||||
ch_out_l <= ch3_buffer;
|
||||
ch_out_r <= ch4_buffer;
|
||||
elsif channel_cnt = 2 then
|
||||
ch_out <= ch3_buffer;
|
||||
ch_out_l <= ch5_buffer;
|
||||
ch_out_r <= ch6_buffer;
|
||||
elsif channel_cnt = 3 then
|
||||
ch_out <= ch4_buffer;
|
||||
elsif channel_cnt = 4 then
|
||||
ch_out <= ch5_buffer;
|
||||
elsif channel_cnt = 5 then
|
||||
ch_out <= ch6_buffer;
|
||||
elsif channel_cnt = 6 then
|
||||
ch_out <= ch7_buffer;
|
||||
elsif channel_cnt = 7 then
|
||||
ch_out <= ch8_buffer;
|
||||
ch_out_l <= ch7_buffer;
|
||||
ch_out_r <= ch8_buffer;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
<File path="src/main_tx.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/aes3rx.vhd" type="file.vhdl" enable="1"/>
|
||||
<File path="src/aes3tx.vhd" type="file.vhdl" enable="1"/>
|
||||
<File path="src/aes3tx2.vhd" type="file.vhdl" enable="1"/>
|
||||
<File path="src/i2s_deser.vhd" type="file.vhdl" enable="1"/>
|
||||
<File path="src/i2s_quad_deserializer.vhd" type="file.vhdl" enable="1"/>
|
||||
<File path="src/i2s_quad_transmitter.vhd" type="file.vhdl" enable="1"/>
|
||||
|
||||
@ -22,6 +22,6 @@
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/test_fpga_project_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/test_fpga_project_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd000000020000000000000186000002cafc0200000002fc00000037000001630000000000fffffffa000000000200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000037000002ca0000006200ffffff000000030000078000000150fc0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000000001190000005100fffffffc0000011d00000663000000a100fffffffa000000000100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008c00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100ffffff000005f6000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
|
||||
<Ui>000000ff00000001fd000000020000000000000186000002c9fc0200000002fc00000037000000ec0000000000fffffffa000000000200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000037000002c90000006200ffffff000000030000078000000151fc0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000000001190000005100fffffffc0000011d00000663000000a100fffffffa000000000100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000008c00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100ffffff000005f6000002c900000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
|
||||
<FpUi>312e30313131000000ff00000000fd00000002000000000000019300000083fc0200000001fc00000037000000830000008301000014fa000000010200000002fb0000001c0044006f0063006b00650072002e00530075006d006d0061007200790100000000ffffffff0000006e00fffffffb0000001c0044006f0063006b00650072002e004e00650074006c0069007300740100000000ffffffff0000005d00ffffff00000003000003c000000262fc0100000001fc00000000000003c00000007900fffffffa00000001010000000bfb0000001c0044006f0063006b00650072002e004d0065007300730061006700650100000000ffffffff0000005900fffffffb0000002c0044006f0063006b00650072002e0049002f004f002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000fffffffb000000380044006f0063006b00650072002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000fffffffb000000360044006f0063006b00650072002e005200650073006f0075007200630065002e005200650073006500720076006100740069006f006e0100000000ffffffff0000005000fffffffb000000300044006f0063006b00650072002e00470072006f00750070002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000fffffffb000000380044006f0063006b00650072002e0043006c006f0063006b002e004e00650074002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000fffffffb000000420044006f0063006b00650072002e00470043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000fffffffb000000420044006f0063006b00650072002e00480043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000fffffffb000000440044006f0063006b00650072002e00470043004c004b0032002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000005000fffffffb000000460044006f0063006b00650072002e00480043004c004b00350041002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000005000fffffffb0000002e0044006f0063006b00650072002e0056007200650066002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000005000ffffff000002290000008300000004000000040000000800000008fc000000010000000200000001000000180054006f006f006c004200610072002e00460069006c00650100000000ffffffff0000000000000000</FpUi>
|
||||
</UserConfig>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user